1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
4 to receive from the video device.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
9 is to receive from the device.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
15 - compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
16 "xlnx,axi-cdma-1.00.a""
17 - #dma-cells: Should be <1>, see "dmas" property below
18 - reg: Should contain DMA registers location and length.
19 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
20 - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
21 - dma-channel child node: Should have at least one channel and can have up to
22 two channels per device. This node specifies the properties of each
23 DMA channel (see child node properties below).
24 - clocks: Input clock specifier. Refer to common clock bindings.
25 - clock-names: List of input clocks
27 Required elements: "s_axi_lite_aclk"
28 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
29 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
31 Required elements: "s_axi_lite_aclk", "m_axi_aclk"
33 Required elements: "s_axi_lite_aclk"
34 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
37 Required properties for VDMA:
38 - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
41 - xlnx,include-sg: Tells configured for Scatter-mode in
43 Optional properties for AXI DMA:
44 - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
45 - xlnx,sg-length-width: Should be set to the width of buffer length register as
46 configured in hardware. If this property is missing or has invalid width
47 i.e not in range of 8-23, maximum buffer length width 23 bits is used.
48 Optional properties for VDMA:
49 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
50 It takes following values:
51 {1}, flush both channels
52 {2}, flush mm2s channel
53 {3}, flush s2mm channel
55 Required child node properties:
57 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
58 "xlnx,axi-vdma-s2mm-channel".
59 For CDMA: It should be "xlnx,axi-cdma-channel".
60 For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
61 "xlnx,axi-dma-s2mm-channel".
62 - interrupts: Should contain per channel VDMA interrupts.
63 - xlnx,datawidth: Should contain the stream data width, take values
66 Optional child node properties:
67 - xlnx,include-dre: Tells hardware is configured for Data
69 Optional child node properties for VDMA:
70 - xlnx,genlock-mode: Tells Genlock synchronization is
71 enabled/disabled in hardware.
72 - xlnx,enable-vert-flip: Tells vertical flip is
73 enabled/disabled in hardware(S2MM path).
74 Optional child node properties for AXI DMA:
75 -dma-channels: Number of dma channels in child node.
80 axi_vdma_0: axivdma@40030000 {
81 compatible = "xlnx,axi-vdma-1.00.a";
83 reg = < 0x40030000 0x10000 >;
84 dma-ranges = <0x00000000 0x00000000 0x40000000>;
85 xlnx,num-fstores = <0x8>;
86 xlnx,flush-fsync = <0x1>;
87 xlnx,addrwidth = <0x20>;
88 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
89 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
90 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
91 dma-channel@40030000 {
92 compatible = "xlnx,axi-vdma-mm2s-channel";
93 interrupts = < 0 54 4 >;
94 xlnx,datawidth = <0x40>;
96 dma-channel@40030030 {
97 compatible = "xlnx,axi-vdma-s2mm-channel";
98 interrupts = < 0 53 4 >;
99 xlnx,datawidth = <0x40>;
107 - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
108 where Channel ID is '0' for write/tx and '1' for read/rx
109 channel if both channels are enabled.
110 If only one channel is enabled either tx or rx the Channel ID is '0'.
111 - dma-names: a list of DMA channel names, one per "dmas" entry
116 vdmatest_0: vdmatest@0 {
117 compatible ="xlnx,axi-vdma-test-1.00.a";
118 dmas = <&axi_vdma_0 0
120 dma-names = "vdma0", "vdma1";