#include <linux/watchdog.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
/* These are temporary values. Need to finalize when we have a fixed clock */
-#define XA9WDT_MAX_TIMEOUT 300
+#define XA9WDT_CLOCK 5000000
+#define XA9WDT_MAX_TIMEOUT 600
#define XA9WDT_DEFAULT_TIMEOUT 10
#define XA9WDT_PRESCALER 00
/**
* xa9wdt_start - Enable and start the watchdog.
*
- * The clock to the WDT is 12.5 MHz and the counter value is calculated
+ * The clock to the WDT is 5 MHz and the counter value is calculated
* according to the formula:
* load count = ((timeout * clock) / (prescalar + 1)) - 1.
* This needs to be re-visited when the PERIPHCLK clock changes in HW.
**/
static void xa9wdt_start(void)
{
- wdt_count = ((wdt_timeout * 12500000) / (XA9WDT_PRESCALER + 1)) - 1;
+ wdt_count = ((wdt_timeout * XA9WDT_CLOCK) / (XA9WDT_PRESCALER + 1)) - 1;
spin_lock(&wdt->io_lock);
xa9wdt_writereg(wdt_count, XA9WDT_LOAD_OFFSET);
*/
if (xa9wdt_settimeout(wdt_timeout)) {
xa9wdt_settimeout(XA9WDT_DEFAULT_TIMEOUT);
- pr_info("xa9wdt: wdt_timeout value limited to 1 - 300 sec, \
- using default %dsec timeout\n", XA9WDT_DEFAULT_TIMEOUT);
+ pr_info("xa9wdt: wdt_timeout value limited to 1 - %d sec, "
+ "using default %dsec timeout\n",
+ XA9WDT_MAX_TIMEOUT, XA9WDT_DEFAULT_TIMEOUT);
}
return platform_driver_register(&xa9wdt_driver);
}
#include <linux/platform_device.h>
#include <linux/slab.h>
-
-#define XWDTPSS_DEFAULT_TIMEOUT 10 /* Supports 1 - 600 sec */
+#define XWDTPSS_CLOCK 2500000
+#define XWDTPSS_DEFAULT_TIMEOUT 10
+#define XWDTPSS_MAX_TIMEOUT 400 /* Supports 1 - 400 sec */
static int wdt_timeout = XWDTPSS_DEFAULT_TIMEOUT;
static int nowayout = WATCHDOG_NOWAYOUT;
/**
* xwdtpss_start - Enable and start the watchdog.
*
- * The clock to the WDT is 100 MHz, the prescalar is set to divide
+ * The clock to the WDT is 2.5 MHz, the prescalar is set to divide
* the clock by 4096 and the counter value is calculated according to
* the formula:
* calculated count = (timeout * clock) / prescalar + 1.
* 64 - Prescalar divide value.
* 0x1000 - Counter Value Divide, to obtain the value of counter
* reset to write to control register.
- * 781250 - Input clock value.
+ * 2500000 - Input clock value.
* This code needs to be modified when the clock value increases
* in H/W.
*/
- count = (wdt_timeout * 781250) / (64 * 0x1000) + 1;
+ count = (wdt_timeout * XWDTPSS_CLOCK) / (64 * 0x1000) + 1;
/* Check for boundary conditions of counter value */
if (count > 0xFFF)
**/
static int xwdtpss_settimeout(int new_time)
{
- if ((new_time <= 0) || (new_time > 600))
+ if ((new_time <= 0) || (new_time > XWDTPSS_MAX_TIMEOUT))
return -ENOTSUPP;
wdt_timeout = new_time;
return 0;
*/
if (xwdtpss_settimeout(wdt_timeout)) {
xwdtpss_settimeout(XWDTPSS_DEFAULT_TIMEOUT);
- pr_info("xwdtpss: wdt_timeout value limited to 1 - 600 sec, "
+ pr_info("xwdtpss: wdt_timeout value limited to 1 - %d sec, "
"using default timeout of %dsec\n",
- XWDTPSS_DEFAULT_TIMEOUT);
+ XWDTPSS_MAX_TIMEOUT, XWDTPSS_DEFAULT_TIMEOUT);
}
return platform_driver_register(&xwdtpss_driver);
}