Sadanand [Fri, 20 Aug 2010 06:15:45 +0000 (11:45 +0530)]
Xilinx: ARM: Watchdog drivers: Fix compiler errors and update clks
This patch fixes compiler errors in the SCU WDT driver and updates
the clock frequencies for the SCU WDT and PSS WDT. These drivers
have been tested on PEEP4
To make it easier without u-boot for SMP booting, like with jtag,
the kernel now writes the CPU1 reset vector. This also keeps all
the hacky code together in the kernel as u-boot changes are not
required at all for booting SMP kernel.
John Linn [Thu, 19 Aug 2010 23:05:19 +0000 (17:05 -0600)]
Xilinx: ARM: Update SMP boot to work with u-boot and boot rom
New code was added to reset CPU1 to get CPU1 out of the wfe state
that the boot rom put it into. This assumes that u-boot or something
like jtag_tcl has put a branch to 0x8000 in address 0 so that CPU1
has a boot vector to get to the kernel.
Without u-boot, a 0xE3a0F902 can be written into address 0 so that
the reset of CPU1 will work.
John Linn [Wed, 11 Aug 2010 21:22:55 +0000 (15:22 -0600)]
Xilinx: ARM: PSS WDT: Updated driver so it will compile
Apparently it wasn't including the right header files and was relying
on some other header to include slab.h and that header no longer does
so it wouldn't compile. This updates it to include slab.h.
Haibing Ma [Mon, 9 Aug 2010 16:10:34 +0000 (10:10 -0600)]
Xilinx: ARM: DMA: 1 8-channel DMAC
Changed the pl330 driver and devices.c so it has 1 8-channel DMAC
changed the irq numbers accordingly
Changed the test so the expected error code matches the the actual one
John Linn [Wed, 4 Aug 2010 14:20:35 +0000 (08:20 -0600)]
Xilinx: ARM: Added new tcl file for PEEP4 initialization
The new file, remap_ddr_peep4.tcl, remaps DDR to 0 and also adds
a new register that is in PEEP4 to map ram up high. This script
should be sourced before runnning u-boot or Linux.
John Linn [Tue, 29 Jun 2010 17:53:31 +0000 (11:53 -0600)]
Xilinx: ARM: Moving peep2 config to be SMP by default
The smp defconfig is now removed so that all peep testing will be
using the smp kernel. SMP can be disabled in the kernel config if
there's any issues.
John Linn [Mon, 28 Jun 2010 14:32:32 +0000 (08:32 -0600)]
Xilinx: ARM: fixing broadcast timer device when no local timers
The initialization of percpu timers was commented out during
previous local timer testing, but this won't work for when
local timers are disabled. The broadcast method when local
timers are disabled require this initialization.
This appears to fix the timing problems I was seeing in the SMP
mode with processes on CPU1 not working with any time requirements.
The sleep command and top both work now on on CPUs.
Jason McMullan [Wed, 5 May 2010 17:59:37 +0000 (18:59 +0100)]
ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310
The L310 cache controller's interface is almost identical
to the L210. One major difference is that the PL310 can
have up to 16 ways.
This change uses the cache's part ID and the Associativity
bits in the AUX_CTRL register to determine the number of ways.
Also, this version prints out the CACHE_ID and AUX_CTRL registers.
Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
John Linn [Mon, 21 Jun 2010 23:28:04 +0000 (17:28 -0600)]
Xilinx: ARM: Updated SMP boot processing to remove hacks
This change cleans up the SMP boot processing and makes it closely
match what it should be based on the ARM model. It does still
incorporate some code that should be moved to a boot loader.
It now uses fixed addresses for the handshaking to the boot loader
code with 2 addresses, one for the address to jump to from the boot
loader, and another to signal when CPU0 is ready for CPU1 to start
the kernel.
John Linn [Sat, 19 Jun 2010 15:58:56 +0000 (09:58 -0600)]
Xilinx: ARM: Prevent timer warnings due to local timers not working
This commit adds conditional compilation to the smp code around the
percpu_timer_init calls so that when local times are disabled, these
functions don't get called. Without this, the timer was giving warnings
when the kernel booted that indicated the clockevents could not switch
to one-shot mode: dummy timer is not functional.
Once local timers are fixed, this code should be removed.
John Linn [Sat, 19 Jun 2010 15:21:31 +0000 (09:21 -0600)]
Xilinx: ARM: Fixing SMP boot on PEEP2
The method used for SMP boot on Palladium didn't work correctly on
PEEP2. When CPU1 was polling for the boot key it seemed to stop
CPU0 from executing the kernel almost like it was being starved of
any throughput on the bus.
A WFE is added to head.S for putting CPU1 into a sleep mode so that
it isn't hogging the bus and CPU0 can boot. It was also necessary
to put an sev instruction into smp.c for CPU0 to wakeup CPU1, but onluy
after writing the key into the boot lock and flushing the caches.
Note it was necessary to put the WFE in CPU1 code in the loop that checks
the boot lock for the key because debug events (most commands in the
JTAG TCL) cause the WFE to wakeup falsely. It's also necessary for CPU1
to write the key and flush BEFORE doing the sev instruction.
John Linn [Sat, 19 Jun 2010 15:17:45 +0000 (09:17 -0600)]
Xilinx: ARM: Updating TTC input clock rate for PEEP2
The input clock is faster so it needs to match the hardware. Prior to
this change the bogoMIPS from the kernel was very low, now it is more
matching the previous DF platform.
John Linn [Sat, 19 Jun 2010 15:11:52 +0000 (09:11 -0600)]
Xilinx: ARM: Moving the kernel back to address 0 for PEEP2
We figured out the issue with DDR such that now it can be mapped to
0 such that the kernel can be mapped at 0. Mapping it at 0 is easier
because it's a direct mapping between virtual and physical (mask the
top nibble from a virtual to get a physical) which makes it easier
to deal with in code.
The SMP code broke when the kernel was moved to 0x208000 because the
key address virtual to physical was no longer a direct mapping.
The following TCL commands should be used prior to loading the kernel
on the PEEP2 design so that DDR is mapped at 0, otherwise the kernel
loading will cause an error when it's most of the way loaded.
John Linn [Wed, 9 Jun 2010 21:19:25 +0000 (15:19 -0600)]
Xilinx: ARM: Updated hardware.h to increase memory
Increased from 23 to 128 Meg thinking it might help the kernel be
faster on the new PEEP. Didn't help that, but seems useful anyway
now that there's more testing on network builds.
John Linn [Tue, 8 Jun 2010 16:09:05 +0000 (10:09 -0600)]
Xilinx: ARM: Adding new defconfig for the new PEEP board (EP107)
For the transition from the Dragonfire EP platform to the new PEEP
platform referred to as EP107, this should make it clearer. It can
go away at some point soon.
The new file, xilinx_ep107_defconfig, also minimizes the kernel
size right now as the platform is really slow. All kernel debug
is turned off to try to help speed it up.
John Linn [Thu, 8 Apr 2010 16:19:47 +0000 (10:19 -0600)]
Add non-Virtex5 support for LL TEMAC driver
This patch adds support for using the LL TEMAC Ethernet driver on
non-Virtex 5 platforms by adding support for accessing the Soft DMA
registers as if they were memory mapped instead of solely through the
DCR's (available on the Virtex 5).
The patch also updates the driver so that it runs on the MicroBlaze.
The changes were tested on the PowerPC 440, PowerPC 405, and the
MicroBlaze platforms.
Signed-off-by: John Tyner <jtyner@cs.ucr.edu> Signed-off-by: John Linn <john.linn@xilinx.com>
John Linn [Mon, 7 Jun 2010 21:01:12 +0000 (15:01 -0600)]
Xilinx: ARM: Adding ability to run kernel on CPU1
This change adds the ability to setup CPU1 to run the kernel while
nothing is running on CPU0. A menu is added under the Xilinx platform
to select it and the GIC is updated to set irqs to be on CPU1.
John Linn [Mon, 7 Jun 2010 20:53:41 +0000 (14:53 -0600)]
Xilinx: ARM: Fix to allow kernel to run on CPU1
The SMP code that was added didn't only affect SMP, but AMP when
trying to run the kernel only on CPU1. This change just prevents
CPU1 from getting stuck in the loop at the front of head which
is designed to catch CPU1 when running SMP.
John Linn [Wed, 2 Jun 2010 23:20:12 +0000 (17:20 -0600)]
Xilinx: ARM: Added the ability to disable the D cache
The kernel always had a config option, but I think the kernel didn't build.
This disables the ldrex/strex instructions so the kernel builds and runs.
This can't be used with SMP.
John Linn [Thu, 3 Jun 2010 23:04:51 +0000 (17:04 -0600)]
Xilinx: ARM: Added def config file for nfs root
This def config file has the command line setup correctly to allow
nfs root to be used to boot the kernel. It also has D cache disabled
since the network is working ok without it on.
John Linn [Wed, 2 Jun 2010 23:20:12 +0000 (17:20 -0600)]
Xilinx: ARM: Added the ability to disable the D cache
The kernel always had a config option, but I think the kernel didn't build.
This disables the ldrex/strex instructions so the kernel builds and runs.
This can't be used with SMP.
Michal Simek [Tue, 4 May 2010 14:43:30 +0000 (16:43 +0200)]
ll_temac: Allocate skb buffer which correspond to mtu size + pad
This patch fix regression on Microblaze which is caused by skb->truesize
which is used in kernel.
Driver can work with actual mtu size and prepared skb buffer for it.
This change also caused that dma_map/unmap operations take less time
because of cache handling.
xenet_change_mtu function close device. Free all preallocated buffers
with old mtu size, enable dma engine, prepared skb buffer with new
mtu size and open it again.
John Linn [Wed, 19 May 2010 20:51:22 +0000 (14:51 -0600)]
Xilinx: ARM: SMP hacks for Palladium early SMP testing
These changes create a kernel that boots on both CPUs. The code
appears to be pretty brittle still as small changes can keep the
kernel from booting all the way and it's not clear why.
Since we don't have any control of the processor right now in
Palladium the problem is hard to debug.
This code has code that should be in a boot loader as the kernel
entry point is holding CPU1 til CPU0 gets thru some initialization
and then signals to let CPU1 go into the kernel also.
A new kernel default configuration file was added to help with SMP
testing (xilinx_palladium_smp_defconfig). I know it's a long name
but it will go anyway one day anyway.
This code does assume a special init code that is a hacked version
of Rob Pelts. It's not cleaned up yet. It basically boots both
CPUs to 0x8000 with some synchronization between them for the SCU
filter initialization as that's where DDR gets valid. Both CPUs
are going thru main.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6:
rtnetlink: make SR-IOV VF interface symmetric
sctp: delete active ICMP proto unreachable timer when free transport
tcp: fix MD5 (RFC2385) support
Linus Torvalds [Sun, 16 May 2010 18:11:31 +0000 (11:11 -0700)]
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
MIPS: Oprofile: Fix Loongson irq handler
MIPS: N32: Use compat version for sys_ppoll.
MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
Wei Yongjun [Sun, 9 May 2010 16:56:07 +0000 (16:56 +0000)]
sctp: delete active ICMP proto unreachable timer when free transport
transport may be free before ICMP proto unreachable timer expire, so
we should delete active ICMP proto unreachable timer when transport
is going away.
Signed-off-by: Wei Yongjun <yjwei@cn.fujitsu.com> Acked-by: Vlad Yasevich <vladislav.yasevich@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Eric Dumazet [Sun, 16 May 2010 07:34:04 +0000 (00:34 -0700)]
tcp: fix MD5 (RFC2385) support
TCP MD5 support uses percpu data for temporary storage. It currently
disables preemption so that same storage cannot be reclaimed by another
thread on same cpu.
We also have to make sure a softirq handler wont try to use also same
context. Various bug reports demonstrated corruptions.
Fix is to disable preemption and BH.
Reported-by: Bhaskar Dutta <bhaskie@gmail.com> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Wu Zhangjin [Thu, 6 May 2010 16:59:46 +0000 (00:59 +0800)]
MIPS: Oprofile: Fix Loongson irq handler
The interrupt enable bit for the performance counters is in the Control
Register $24, not in the counter register.
loongson2_perfcount_handler(), we need to use
Shane McDonald [Fri, 7 May 2010 05:26:57 +0000 (23:26 -0600)]
MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
are not currently writeable by the ctc1 instruction. In odd corner cases,
this can cause problems. For example, a case existed where a divide-by-zero
exception was generated by the FPU, and the signal handler attempted to
restore the FPU registers to their state before the exception occurred. In
this particular setup, writing the old value to the FCSR register would
cause another divide-by-zero exception to occur immediately. The solution
is to change the ctc1 instruction emulator code to allow the Cause bits of
the FCSR register to be writeable. This is the behaviour of the hardware
that the code is emulating.
This problem was found by Shane McDonald, but the credit for the fix goes
to Kevin Kissell. In Kevin's words:
I submit that the bug is indeed in that ctc_op: case of the emulator. The
Cause bits (17:12) are supposed to be writable by that instruction, but the
CTC1 emulation won't let them be updated by the instruction. I think that
actually if you just completely removed lines 387-388 [...] things would
work a good deal better. At least, it would be a more accurate emulation of
the architecturally defined FPU. If I wanted to be really, really pedantic
(which I sometimes do), I'd also protect the reserved bits that aren't
necessarily writable.
Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
To: anemo@mba.ocn.ne.jp
To: kevink@paralogos.com
To: sshtylyov@mvista.com
Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Nicolas Ferre [Sat, 15 May 2010 16:32:31 +0000 (12:32 -0400)]
mmc: at91_mci: modify cache flush routines
As we were using an internal dma flushing routine, this patch changes to
the DMA API flush_kernel_dcache_page(). Driver is able to compile now.
[akpm@linux-foundation.org: flush_kernel_dcache_page() comes before kunmap_atomic()] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sat, 15 May 2010 16:03:15 +0000 (09:03 -0700)]
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6:
JFS: Free sbi memory in error path
fs/sysv: dereferencing ERR_PTR()
Fix double-free in logfs
Fix the regression created by "set S_DEAD on unlink()..." commit
Linus Torvalds [Sat, 15 May 2010 16:03:02 +0000 (09:03 -0700)]
Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
perf record: Add a fallback to the reference relocation symbol
Jan Blunck [Mon, 12 Apr 2010 23:44:08 +0000 (16:44 -0700)]
JFS: Free sbi memory in error path
I spotted the missing kfree() while removing the BKL.
[akpm@linux-foundation.org: avoid multiple returns so it doesn't happen again] Signed-off-by: Jan Blunck <jblunck@suse.de> Cc: Dave Kleikamp <shaggy@austin.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Fri, 30 Apr 2010 21:17:09 +0000 (17:17 -0400)]
Fix the regression created by "set S_DEAD on unlink()..." commit
1) i_flags simply doesn't work for mount/unlink race prevention;
we may have many links to file and rm on one of those obviously
shouldn't prevent bind on top of another later on. To fix it
right way we need to mark _dentry_ as unsuitable for mounting
upon; new flag (DCACHE_CANT_MOUNT) is protected by d_flags and
i_mutex on the inode in question. Set it (with dont_mount(dentry))
in unlink/rmdir/etc., check (with cant_mount(dentry)) in places
in namespace.c that used to check for S_DEAD. Setting S_DEAD
is still needed in places where we used to set it (for directories
getting killed), since we rely on it for readdir/rmdir race
prevention.
2) rename()/mount() protection has another bogosity - we unhash
the target before we'd checked that it's not a mountpoint. Fixed.
3) ancient bogosity in pivot_root() - we locked i_mutex on the
right directory, but checked S_DEAD on the different (and wrong)
one. Noticed and fixed.
Linus Torvalds [Sat, 15 May 2010 04:28:42 +0000 (21:28 -0700)]
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6126/1: ARM mpcore_wdt: fix build failure and other fixes
ARM: 6125/1: ARM TWD: move TWD registers to common header
ARM: 6110/1: Fix Thumb-2 kernel builds when UACCESS_WITH_MEMCPY is enabled
ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP
ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache ops
ARM: 6106/1: Implement copy_to_user_page() for noMMU
ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.c
Hugh Dickins [Sat, 15 May 2010 02:44:10 +0000 (19:44 -0700)]
profile: fix stats and data leakage
If the kernel is large or the profiling step small, /proc/profile
leaks data and readprofile shows silly stats, until readprofile -r
has reset the buffer: clear the prof_buffer when it is vmalloc()ed.
H. Peter Anvin [Fri, 14 May 2010 20:55:57 +0000 (13:55 -0700)]
x86, mrst: Don't blindly access extended config space
Do not blindly access extended configuration space unless we actively
know we're on a Moorestown platform. The fixed-size BAR capability
lives in the extended configuration space, and thus is not applicable
if the configuration space isn't appropriately sized.
This fixes booting certain VMware configurations with CONFIG_MRST=y.
Moorestown will add a fake PCI-X 266 capability to advertise the
presence of extended configuration space.
Reported-and-tested-by: Petr Vandrovec <petr@vandrovec.name> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Acked-by: Jacob Pan <jacob.jun.pan@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
LKML-Reference: <AANLkTiltKUa3TrKR1M51eGw8FLNoQJSLT0k0_K5X3-OJ@mail.gmail.com>
Linus Torvalds [Fri, 14 May 2010 19:20:09 +0000 (12:20 -0700)]
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments
x86, k8: Fix build error when K8_NB is disabled
x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs
x86: Fix fake apicid to node mapping for numa emulation