tty: serial: uartlite: Specify time for sending chars

Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.

Make this time delay not to be cpu speed dependent.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
index 5f90ef24d475ff728777c63fe32c7ea97adc6485..723a6b79cd14f9ba9370c52e8794003fd52b9443 100644 (file)
--- a/drivers/tty/serial/uartlite.c
+++ b/drivers/tty/serial/uartlite.c
@@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
 static void ulite_console_wait_tx(struct uart_port *port)
 {
-       int i;
        u8 val;
+       unsigned long timeout;
 
        /* Spin waiting for TX fifo to have space available */
-       for (i = 0; i < 100000; i++) {
+       timeout = jiffies + msecs_to_jiffies(1000);
+       while (1) {
                val = uart_in32(ULITE_STATUS, port);
                if ((val & ULITE_STATUS_TXFULL) == 0)
                        break;
+               if (time_after(jiffies, timeout)) {
+                       dev_warn(port->dev,
+                                "timeout waiting for TX buffer empty\n");
+                       break;
+               }
                cpu_relax();
        }
 }