]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
tty: serial: uartlite: Specify time for sending chars
authorMichal Simek <michal.simek@xilinx.com>
Mon, 5 May 2014 14:03:55 +0000 (16:03 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 5 May 2014 14:43:44 +0000 (16:43 +0200)
commit91b7b1df228c1104c15f3489fdbf94b2a1edd8e2
tree860f20955346a5ecabf657a4debc039bc37f415f
parent9cbf15cef3d29f497467e36c21ca62a6ca2710f2
tty: serial: uartlite: Specify time for sending chars

Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.

Make this time delay not to be cpu speed dependent.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/tty/serial/uartlite.c