1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Scene Change Detection driver
5 * Copyright (C) 2018 Xilinx, Inc.
7 * Authors: Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
8 * Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
11 #ifndef _XILINX_SCENECHANGE_H_
12 #define _XILINX_SCENECHANGE_H_
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/dmaengine.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/xilinx-v4l2-controls.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-subdev.h>
30 #include "../../../dma/dmaengine.h"
32 /* Register/Descriptor Offsets */
33 #define XSCD_CTRL_OFFSET 0x000
34 #define XSCD_CTRL_AP_START BIT(0)
35 #define XSCD_CTRL_AP_DONE BIT(1)
36 #define XSCD_CTRL_AP_IDLE BIT(2)
37 #define XSCD_CTRL_AP_READY BIT(3)
38 #define XSCD_CTRL_AUTO_RESTART BIT(7)
40 #define XSCD_GIE_OFFSET 0x004
41 #define XSCD_GIE_EN BIT(0)
43 #define XSCD_IE_OFFSET 0x008
44 #define XSCD_IE_AP_DONE BIT(0)
45 #define XSCD_IE_AP_READY BIT(1)
47 #define XSCD_ISR_OFFSET 0x00c
48 #define XSCD_WIDTH_OFFSET 0x010
49 #define XSCD_HEIGHT_OFFSET 0x018
50 #define XSCD_STRIDE_OFFSET 0x020
51 #define XSCD_VID_FMT_OFFSET 0x028
52 #define XSCD_VID_FMT_RGB 0
53 #define XSCD_VID_FMT_YUV_444 1
54 #define XSCD_VID_FMT_YUV_422 2
55 #define XSCD_VID_FMT_YUV_420 3
56 #define XSCD_VID_FMT_Y8 24
57 #define XSCD_VID_FMT_Y10 25
59 #define XSCD_SUBSAMPLE_OFFSET 0x030
60 #define XSCD_SAD_OFFSET 0x038
61 #define XSCD_ADDR_OFFSET 0x040
62 #define XSCD_CHAN_OFFSET 0x100
63 #define XSCD_CHAN_EN_OFFSET 0x780
65 #define XSCD_MAX_CHANNELS 8
67 /****************************** PROTOTYPES ************************************/
68 #define to_xilinx_chan(chan) \
69 container_of(chan, struct xscd_dma_chan, common)
70 #define to_dma_tx_descriptor(tx) \
71 container_of(tx, struct xscd_dma_tx_descriptor, async_tx)
74 * struct xscd_shared_data - Data to be shared among v4l subdev and DMA engine
75 * @iomem: device I/O register space remapped to kernel virtual memory
76 * @dma_chan_list: List of DMA channels available
77 * @active_streams: Number of active streams
78 * @memory_based: Flag to identify memory based mode
80 struct xscd_shared_data {
82 struct xscd_dma_chan *dma_chan_list[XSCD_MAX_CHANNELS];
88 * struct xscd_device - Xilinx Scene Change Detection device structure
89 * @iomem: device I/O register space remapped to kernel virtual memory
90 * @numstreams: Number of streams in the design
93 * @rst_gpio: reset GPIO
94 * @clk: video core clock
95 * @dma_device: DMA device pointer
96 * @shared_data: Data Shared across devices
97 * @dma_node: DMA device node
98 * @subdevs: subdev device instance
105 struct gpio_desc *rst_gpio;
107 struct platform_device *dma_device;
108 struct xscd_shared_data shared_data;
109 struct device_node *dma_node;
110 struct platform_device *subdevs[XSCD_MAX_CHANNELS];
114 * struct xscd_dma_desc - DMA channel
115 * @luma_plane_addr: Luma plane buffer address
116 * @vsize: width of the luma frame
117 * @hsize: height of the luma frame
118 * @stride: stride of the luma frame
120 struct xscd_dma_desc {
121 dma_addr_t luma_plane_addr;
128 * struct xscd_dma_tx_descriptor - Per Transaction structure
129 * @async_tx: Async transaction descriptor
130 * @sw: Software Descriptor
131 * @node: Node in the channel descriptor list
133 struct xscd_dma_tx_descriptor {
134 struct dma_async_tx_descriptor async_tx;
135 struct xscd_dma_desc sw;
136 struct list_head node;
140 * struct xscd_dma_chan - DMA Channel structure
141 * @xdev: DMA engine driver specific device structure
142 * @iomem: device I/O register space remapped to kernel virtual memory
143 * @lock: Descriptor operation lock
144 * @chan_node: Member of a list of framebuffer channel instances
145 * @pending_list: Descriptors waiting
146 * @done_list: Complete descriptors
147 * @staged_desc: Next buffer to be programmed
148 * @active_desc: Currently active buffer being read/written to
149 * @common: DMA common channel
150 * @dev: The dma device
151 * @idle: Channel idle state
152 * @tasklet: Cleanup work after irq
153 * @id: scene change channel ID
154 * @en: Channel is enabled
155 * @valid_interrupt: Valid interrupt for the channel
157 struct xscd_dma_chan {
158 struct xscd_dma_device *xdev;
161 /* Descriptor operation Lock */
163 struct list_head chan_node;
164 struct list_head pending_list;
165 struct list_head done_list;
166 struct xscd_dma_tx_descriptor *staged_desc;
167 struct xscd_dma_tx_descriptor *active_desc;
168 struct dma_chan common;
171 struct tasklet_struct tasklet;
174 bool valid_interrupt;
178 * struct xscd_chan - Video Stream structure
180 * @id: scene change channel ID
181 * @iomem: device I/O register space remapped to kernel virtual memory
183 * @subdev: V4L2 subdevice
185 * @format: active V4L2 media bus format for the pad
186 * @event: scene change event
187 * @dmachan: dma channel part of the scenechange stream
188 * @lock: lock to protect active stream count variable
195 struct v4l2_subdev subdev;
196 struct media_pad *pad;
197 struct v4l2_mbus_framefmt format;
198 struct v4l2_event event;
199 struct xscd_dma_chan dmachan;
201 /* Lock to protect active stream count */
205 static inline struct xscd_chan *to_chan(struct v4l2_subdev *subdev)
207 return container_of(subdev, struct xscd_chan, subdev);
211 * Register related operations
213 static inline u32 xscd_read(void __iomem *iomem, u32 addr)
215 return ioread32(iomem + addr);
218 static inline void xscd_write(void __iomem *iomem, u32 addr, u32 value)
220 iowrite32(value, iomem + addr);
223 static inline void xscd_clr(void __iomem *iomem, u32 addr, u32 clr)
225 xscd_write(iomem, addr, xscd_read(iomem, addr) & ~clr);
228 static inline void xscd_set(void __iomem *iomem, u32 addr, u32 set)
230 xscd_write(iomem, addr, xscd_read(iomem, addr) | set);
233 struct xscd_dma_tx_descriptor *
234 xscd_dma_alloc_tx_descriptor(struct xscd_dma_chan *chan);
235 void xscd_dma_start_transfer(struct xscd_dma_chan *chan);
236 void xscd_dma_start(struct xscd_dma_chan *chan);
237 void xscd_dma_chan_enable(struct xscd_dma_chan *chan, int chan_en);
238 void xscd_dma_reset(struct xscd_dma_chan *chan);
239 void xscd_dma_halt(struct xscd_dma_chan *chan);
240 void xscd_dma_free_desc_list(struct xscd_dma_chan *chan,
241 struct list_head *list);
242 void xscd_dma_free_descriptors(struct xscd_dma_chan *chan);
243 dma_cookie_t xscd_dma_tx_submit(struct dma_async_tx_descriptor *tx);
244 void xscd_dma_chan_desc_cleanup(struct xscd_dma_chan *chan);
245 void xscd_dma_chan_remove(struct xscd_dma_chan *chan);