1 Xilinx Axi Uartlite controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Can be either of
6 "xlnx,xps-uartlite-1.00.a"
7 "xlnx,opb-uartlite-1.00.b"
8 - reg : Physical base address and size of the Axi Uartlite
10 - interrupts : Property with a value describing the interrupt
12 - interrupt-parent : Must be core interrupt controller.
15 - port-number : Set Uart port number
16 - clock-names : Should be "s_axi_aclk"
17 - clocks : Input clock specifier. Refer to common clock bindings.
21 compatible = "xlnx,xps-uartlite-1.00.a";
22 reg = <0x0 0x800c0000 0x10000>;
23 interrupt-parent = <&gic>;
24 interrupts = <0x0 0x6e 0x1>;