misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value

The AXIS_ENABLE register has 6 bits not 5, change value of AXIS_ENABLE_MASK
from 0x1f to 0x3f.

Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c
index eb09fdea23fc2c7c811e271736aa88fe7e08ea10..b28562b754a943eccfa8c7131386b976d4358606 100644 (file)
--- a/drivers/misc/xilinx_sdfec.c
+++ b/drivers/misc/xilinx_sdfec.c
@@ -52,7 +52,7 @@ static dev_t xsdfec_devt;
 #define XSDFEC_ACTIVE_ADDR                     (0x00008)
 #define XSDFEC_AXIS_WIDTH_ADDR                 (0x0000c)
 #define XSDFEC_AXIS_ENABLE_ADDR                        (0x00010)
-#define XSDFEC_AXIS_ENABLE_MASK                        (0x0001F)
+#define XSDFEC_AXIS_ENABLE_MASK                        (0x0003F)
 #define XSDFEC_FEC_CODE_ADDR                   (0x00014)
 #define XSDFEC_ORDER_ADDR                      (0x00018)