arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  17
  18 / {
  19         compatible = "xlnx,zynqmp";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@0 {
  28                         compatible = "arm,cortex-a53", "arm,armv8";
  29                         device_type = "cpu";
  30                         enable-method = "psci";
  31                         operating-points-v2 = <&cpu_opp_table>;
  32                         reg = <0x0>;
  33                         cpu-idle-states = <&CPU_SLEEP_0>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         compatible = "arm,cortex-a53", "arm,armv8";
  38                         device_type = "cpu";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                         operating-points-v2 = <&cpu_opp_table>;
  42                         cpu-idle-states = <&CPU_SLEEP_0>;
  43                 };
  44
  45                 cpu2: cpu@2 {
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         reg = <0x2>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                         cpu-idle-states = <&CPU_SLEEP_0>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         compatible = "arm,cortex-a53", "arm,armv8";
  56                         device_type = "cpu";
  57                         enable-method = "psci";
  58                         reg = <0x3>;
  59                         operating-points-v2 = <&cpu_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP_0>;
  61                 };
  62
  63                 idle-states {
  64                         entry-method = "psci";
  65
  66                         CPU_SLEEP_0: cpu-sleep-0 {
  67                                 compatible = "arm,idle-state";
  68                                 arm,psci-suspend-param = <0x40000000>;
  69                                 local-timer-stop;
  70                                 entry-latency-us = <300>;
  71                                 exit-latency-us = <600>;
  72                                 min-residency-us = <10000>;
  73                         };
  74                 };
  75         };
  76
  77         cpu_opp_table: cpu_opp_table {
  78                 compatible = "operating-points-v2";
  79                 opp-shared;
  80                 opp00 {
  81                         opp-hz = /bits/ 64 <1199999988>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <500000>;
  84                 };
  85                 opp01 {
  86                         opp-hz = /bits/ 64 <599999994>;
  87                         opp-microvolt = <1000000>;
  88                         clock-latency-ns = <500000>;
  89                 };
  90                 opp02 {
  91                         opp-hz = /bits/ 64 <399999996>;
  92                         opp-microvolt = <1000000>;
  93                         clock-latency-ns = <500000>;
  94                 };
  95                 opp03 {
  96                         opp-hz = /bits/ 64 <299999997>;
  97                         opp-microvolt = <1000000>;
  98                         clock-latency-ns = <500000>;
  99                 };
 100         };
 101
 102         dcc: dcc {
 103                 compatible = "arm,dcc";
 104                 status = "disabled";
 105                 u-boot,dm-pre-reloc;
 106         };
 107
 108         zynqmp_ipi {
 109                 compatible = "xlnx,zynqmp-ipi-mailbox";
 110                 interrupt-parent = <&gic>;
 111                 interrupts = <0 35 4>;
 112                 xlnx,ipi-id = <0>;
 113                 #address-cells = <2>;
 114                 #size-cells = <2>;
 115                 ranges;
 116
 117                 ipi_mailbox_pmu1: mailbox@ff990400 {
 118                         reg = <0x0 0xff9905c0 0x0 0x20>,
 119                               <0x0 0xff9905e0 0x0 0x20>,
 120                               <0x0 0xff990e80 0x0 0x20>,
 121                               <0x0 0xff990ea0 0x0 0x20>;
 122                         reg-names = "local_request_region", "local_response_region",
 123                                     "remote_request_region", "remote_response_region";
 124                         #mbox-cells = <1>;
 125                         xlnx,ipi-id = <4>;
 126                 };
 127         };
 128
 129         pmu {
 130                 compatible = "arm,armv8-pmuv3";
 131                 interrupt-parent = <&gic>;
 132                 interrupts = <0 143 4>,
 133                              <0 144 4>,
 134                              <0 145 4>,
 135                              <0 146 4>;
 136         };
 137
 138         psci {
 139                 compatible = "arm,psci-0.2";
 140                 method = "smc";
 141         };
 142
 143         firmware {
 144                 zynqmp_firmware: zynqmp-firmware {
 145                         compatible = "xlnx,zynqmp-firmware";
 146                         method = "smc";
 147                         #power-domain-cells = <0x1>;
 148                         u-boot,dm-pre-reloc;
 149
 150                         zynqmp_power: zynqmp-power {
 151                                 compatible = "xlnx,zynqmp-power";
 152                                 interrupt-parent = <&gic>;
 153                                 interrupts = <0 35 4>;
 154                                 mboxes = <&ipi_mailbox_pmu1 0>,
 155                                          <&ipi_mailbox_pmu1 1>;
 156                                 mbox-names = "tx", "rx";
 157                         };
 158
 159                         zynqmp_reset: reset-controller {
 160                                 compatible = "xlnx,zynqmp-reset";
 161                                 #reset-cells = <1>;
 162                         };
 163
 164                         pinctrl0: pinctrl {
 165                                 compatible = "xlnx,zynqmp-pinctrl";
 166                                 status = "disabled";
 167                         };
 168                 };
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupt-parent = <&gic>;
 174                 interrupts = <1 13 0xf08>,
 175                              <1 14 0xf08>,
 176                              <1 11 0xf08>,
 177                              <1 10 0xf08>;
 178         };
 179
 180         edac {
 181                 compatible = "arm,cortex-a53-edac";
 182         };
 183
 184         fpga_full: fpga-full {
 185                 compatible = "fpga-region";
 186                 fpga-mgr = <&pcap>;
 187                 #address-cells = <2>;
 188                 #size-cells = <2>;
 189         };
 190
 191         nvmem_firmware {
 192                 compatible = "xlnx,zynqmp-nvmem-fw";
 193                 #address-cells = <1>;
 194                 #size-cells = <1>;
 195
 196                 soc_revision: soc_revision@0 {
 197                         reg = <0x0 0x4>;
 198                 };
 199                 /* efuse access */
 200                 efuse_dna: efuse_dna@c {
 201                         reg = <0xc 0xc>;
 202                 };
 203                 efuse_usr0: efuse_usr0@20 {
 204                         reg = <0x20 0x4>;
 205                 };
 206                 efuse_usr1: efuse_usr1@24 {
 207                         reg = <0x24 0x4>;
 208                 };
 209                 efuse_usr2: efuse_usr2@28 {
 210                         reg = <0x28 0x4>;
 211                 };
 212                 efuse_usr3: efuse_usr3@2c {
 213                         reg = <0x2c 0x4>;
 214                 };
 215                 efuse_usr4: efuse_usr4@30 {
 216                         reg = <0x30 0x4>;
 217                 };
 218                 efuse_usr5: efuse_usr5@34 {
 219                         reg = <0x34 0x4>;
 220                 };
 221                 efuse_usr6: efuse_usr6@38 {
 222                         reg = <0x38 0x4>;
 223                 };
 224                 efuse_usr7: efuse_usr7@3c {
 225                         reg = <0x3c 0x4>;
 226                 };
 227                 efuse_miscusr: efuse_miscusr@40 {
 228                         reg = <0x40 0x4>;
 229                 };
 230                 efuse_chash: efuse_chash@50 {
 231                         reg = <0x50 0x4>;
 232                 };
 233                 efuse_pufmisc: efuse_pufmisc@54 {
 234                         reg = <0x54 0x4>;
 235                 };
 236                 efuse_sec: efuse_sec@58 {
 237                         reg = <0x58 0x4>;
 238                 };
 239                 efuse_spkid: efuse_spkid@5c {
 240                         reg = <0x5c 0x4>;
 241                 };
 242                 efuse_ppk0hash: efuse_ppk0hash@a0 {
 243                         reg = <0xa0 0x30>;
 244                 };
 245                 efuse_ppk1hash: efuse_ppk1hash@d0 {
 246                         reg = <0xd0 0x30>;
 247                 };
 248         };
 249
 250         pcap: pcap {
 251                 compatible = "xlnx,zynqmp-pcap-fpga";
 252                 clock-names = "ref_clk";
 253         };
 254
 255         xlnx_rsa: zynqmp_rsa {
 256                 compatible = "xlnx,zynqmp-rsa";
 257         };
 258
 259         xlnx_keccak_384: sha384 {
 260                 compatible = "xlnx,zynqmp-keccak-384";
 261         };
 262
 263         xlnx_aes: zynqmp_aes {
 264                 compatible = "xlnx,zynqmp-aes";
 265         };
 266
 267         amba_apu: amba_apu@0 {
 268                 compatible = "simple-bus";
 269                 #address-cells = <2>;
 270                 #size-cells = <1>;
 271                 ranges = <0 0 0 0 0xffffffff>;
 272
 273                 gic: interrupt-controller@f9010000 {
 274                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 275                         #interrupt-cells = <3>;
 276                         reg = <0x0 0xf9010000 0x10000>,
 277                               <0x0 0xf9020000 0x20000>,
 278                               <0x0 0xf9040000 0x20000>,
 279                               <0x0 0xf9060000 0x20000>;
 280                         interrupt-controller;
 281                         interrupt-parent = <&gic>;
 282                         interrupts = <1 9 0xf04>;
 283                 };
 284         };
 285
 286         smmu: smmu@fd800000 {
 287                 compatible = "arm,mmu-500";
 288                 reg = <0x0 0xfd800000 0x0 0x20000>;
 289                 #iommu-cells = <1>;
 290                 status = "disabled";
 291                 #global-interrupts = <1>;
 292                 interrupt-parent = <&gic>;
 293                 interrupts = <0 155 4>,
 294                         <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 295                         <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 296                         <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 297                         <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 298         };
 299
 300         amba: amba {
 301                 compatible = "simple-bus";
 302                 u-boot,dm-pre-reloc;
 303                 #address-cells = <2>;
 304                 #size-cells = <2>;
 305                 ranges;
 306
 307                 can0: can@ff060000 {
 308                         compatible = "xlnx,zynq-can-1.0";
 309                         status = "disabled";
 310                         clock-names = "can_clk", "pclk";
 311                         reg = <0x0 0xff060000 0x0 0x1000>;
 312                         interrupts = <0 23 4>;
 313                         interrupt-parent = <&gic>;
 314                         tx-fifo-depth = <0x40>;
 315                         rx-fifo-depth = <0x40>;
 316                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 317                 };
 318
 319                 can1: can@ff070000 {
 320                         compatible = "xlnx,zynq-can-1.0";
 321                         status = "disabled";
 322                         clock-names = "can_clk", "pclk";
 323                         reg = <0x0 0xff070000 0x0 0x1000>;
 324                         interrupts = <0 24 4>;
 325                         interrupt-parent = <&gic>;
 326                         tx-fifo-depth = <0x40>;
 327                         rx-fifo-depth = <0x40>;
 328                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 329                 };
 330
 331                 cci: cci@fd6e0000 {
 332                         compatible = "arm,cci-400";
 333                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 334                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 335                         #address-cells = <1>;
 336                         #size-cells = <1>;
 337
 338                         pmu@9000 {
 339                                 compatible = "arm,cci-400-pmu,r1";
 340                                 reg = <0x9000 0x5000>;
 341                                 interrupt-parent = <&gic>;
 342                                 interrupts = <0 123 4>,
 343                                              <0 123 4>,
 344                                              <0 123 4>,
 345                                              <0 123 4>,
 346                                              <0 123 4>;
 347                         };
 348                 };
 349
 350                 /* GDMA */
 351                 fpd_dma_chan1: dma@fd500000 {
 352                         status = "disabled";
 353                         compatible = "xlnx,zynqmp-dma-1.0";
 354                         reg = <0x0 0xfd500000 0x0 0x1000>;
 355                         interrupt-parent = <&gic>;
 356                         interrupts = <0 124 4>;
 357                         clock-names = "clk_main", "clk_apb";
 358                         xlnx,bus-width = <128>;
 359                         #stream-id-cells = <1>;
 360                         iommus = <&smmu 0x14e8>;
 361                         power-domains = <&zynqmp_firmware PD_GDMA>;
 362                 };
 363
 364                 fpd_dma_chan2: dma@fd510000 {
 365                         status = "disabled";
 366                         compatible = "xlnx,zynqmp-dma-1.0";
 367                         reg = <0x0 0xfd510000 0x0 0x1000>;
 368                         interrupt-parent = <&gic>;
 369                         interrupts = <0 125 4>;
 370                         clock-names = "clk_main", "clk_apb";
 371                         xlnx,bus-width = <128>;
 372                         #stream-id-cells = <1>;
 373                         iommus = <&smmu 0x14e9>;
 374                         power-domains = <&zynqmp_firmware PD_GDMA>;
 375                 };
 376
 377                 fpd_dma_chan3: dma@fd520000 {
 378                         status = "disabled";
 379                         compatible = "xlnx,zynqmp-dma-1.0";
 380                         reg = <0x0 0xfd520000 0x0 0x1000>;
 381                         interrupt-parent = <&gic>;
 382                         interrupts = <0 126 4>;
 383                         clock-names = "clk_main", "clk_apb";
 384                         xlnx,bus-width = <128>;
 385                         #stream-id-cells = <1>;
 386                         iommus = <&smmu 0x14ea>;
 387                         power-domains = <&zynqmp_firmware PD_GDMA>;
 388                 };
 389
 390                 fpd_dma_chan4: dma@fd530000 {
 391                         status = "disabled";
 392                         compatible = "xlnx,zynqmp-dma-1.0";
 393                         reg = <0x0 0xfd530000 0x0 0x1000>;
 394                         interrupt-parent = <&gic>;
 395                         interrupts = <0 127 4>;
 396                         clock-names = "clk_main", "clk_apb";
 397                         xlnx,bus-width = <128>;
 398                         #stream-id-cells = <1>;
 399                         iommus = <&smmu 0x14eb>;
 400                         power-domains = <&zynqmp_firmware PD_GDMA>;
 401                 };
 402
 403                 fpd_dma_chan5: dma@fd540000 {
 404                         status = "disabled";
 405                         compatible = "xlnx,zynqmp-dma-1.0";
 406                         reg = <0x0 0xfd540000 0x0 0x1000>;
 407                         interrupt-parent = <&gic>;
 408                         interrupts = <0 128 4>;
 409                         clock-names = "clk_main", "clk_apb";
 410                         xlnx,bus-width = <128>;
 411                         #stream-id-cells = <1>;
 412                         iommus = <&smmu 0x14ec>;
 413                         power-domains = <&zynqmp_firmware PD_GDMA>;
 414                 };
 415
 416                 fpd_dma_chan6: dma@fd550000 {
 417                         status = "disabled";
 418                         compatible = "xlnx,zynqmp-dma-1.0";
 419                         reg = <0x0 0xfd550000 0x0 0x1000>;
 420                         interrupt-parent = <&gic>;
 421                         interrupts = <0 129 4>;
 422                         clock-names = "clk_main", "clk_apb";
 423                         xlnx,bus-width = <128>;
 424                         #stream-id-cells = <1>;
 425                         iommus = <&smmu 0x14ed>;
 426                         power-domains = <&zynqmp_firmware PD_GDMA>;
 427                 };
 428
 429                 fpd_dma_chan7: dma@fd560000 {
 430                         status = "disabled";
 431                         compatible = "xlnx,zynqmp-dma-1.0";
 432                         reg = <0x0 0xfd560000 0x0 0x1000>;
 433                         interrupt-parent = <&gic>;
 434                         interrupts = <0 130 4>;
 435                         clock-names = "clk_main", "clk_apb";
 436                         xlnx,bus-width = <128>;
 437                         #stream-id-cells = <1>;
 438                         iommus = <&smmu 0x14ee>;
 439                         power-domains = <&zynqmp_firmware PD_GDMA>;
 440                 };
 441
 442                 fpd_dma_chan8: dma@fd570000 {
 443                         status = "disabled";
 444                         compatible = "xlnx,zynqmp-dma-1.0";
 445                         reg = <0x0 0xfd570000 0x0 0x1000>;
 446                         interrupt-parent = <&gic>;
 447                         interrupts = <0 131 4>;
 448                         clock-names = "clk_main", "clk_apb";
 449                         xlnx,bus-width = <128>;
 450                         #stream-id-cells = <1>;
 451                         iommus = <&smmu 0x14ef>;
 452                         power-domains = <&zynqmp_firmware PD_GDMA>;
 453                 };
 454
 455                 gpu: gpu@fd4b0000 {
 456                         status = "disabled";
 457                         compatible = "arm,mali-400", "arm,mali-utgard";
 458                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 459                         interrupt-parent = <&gic>;
 460                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 461                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 462                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 463                         power-domains = <&zynqmp_firmware PD_GPU>;
 464                 };
 465
 466                 /* LPDDMA default allows only secured access. inorder to enable
 467                  * These dma channels, Users should ensure that these dma
 468                  * Channels are allowed for non secure access.
 469                  */
 470                 lpd_dma_chan1: dma@ffa80000 {
 471                         status = "disabled";
 472                         compatible = "xlnx,zynqmp-dma-1.0";
 473                         reg = <0x0 0xffa80000 0x0 0x1000>;
 474                         interrupt-parent = <&gic>;
 475                         interrupts = <0 77 4>;
 476                         clock-names = "clk_main", "clk_apb";
 477                         xlnx,bus-width = <64>;
 478                         #stream-id-cells = <1>;
 479                         /* iommus = <&smmu 0x868>; */
 480                         power-domains = <&zynqmp_firmware PD_ADMA>;
 481                 };
 482
 483                 lpd_dma_chan2: dma@ffa90000 {
 484                         status = "disabled";
 485                         compatible = "xlnx,zynqmp-dma-1.0";
 486                         reg = <0x0 0xffa90000 0x0 0x1000>;
 487                         interrupt-parent = <&gic>;
 488                         interrupts = <0 78 4>;
 489                         clock-names = "clk_main", "clk_apb";
 490                         xlnx,bus-width = <64>;
 491                         #stream-id-cells = <1>;
 492                         /* iommus = <&smmu 0x869>; */
 493                         power-domains = <&zynqmp_firmware PD_ADMA>;
 494                 };
 495
 496                 lpd_dma_chan3: dma@ffaa0000 {
 497                         status = "disabled";
 498                         compatible = "xlnx,zynqmp-dma-1.0";
 499                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 500                         interrupt-parent = <&gic>;
 501                         interrupts = <0 79 4>;
 502                         clock-names = "clk_main", "clk_apb";
 503                         xlnx,bus-width = <64>;
 504                         #stream-id-cells = <1>;
 505                         /* iommus = <&smmu 0x86a>; */
 506                         power-domains = <&zynqmp_firmware PD_ADMA>;
 507                 };
 508
 509                 lpd_dma_chan4: dma@ffab0000 {
 510                         status = "disabled";
 511                         compatible = "xlnx,zynqmp-dma-1.0";
 512                         reg = <0x0 0xffab0000 0x0 0x1000>;
 513                         interrupt-parent = <&gic>;
 514                         interrupts = <0 80 4>;
 515                         clock-names = "clk_main", "clk_apb";
 516                         xlnx,bus-width = <64>;
 517                         #stream-id-cells = <1>;
 518                         /* iommus = <&smmu 0x86b>; */
 519                         power-domains = <&zynqmp_firmware PD_ADMA>;
 520                 };
 521
 522                 lpd_dma_chan5: dma@ffac0000 {
 523                         status = "disabled";
 524                         compatible = "xlnx,zynqmp-dma-1.0";
 525                         reg = <0x0 0xffac0000 0x0 0x1000>;
 526                         interrupt-parent = <&gic>;
 527                         interrupts = <0 81 4>;
 528                         clock-names = "clk_main", "clk_apb";
 529                         xlnx,bus-width = <64>;
 530                         #stream-id-cells = <1>;
 531                         /* iommus = <&smmu 0x86c>; */
 532                         power-domains = <&zynqmp_firmware PD_ADMA>;
 533                 };
 534
 535                 lpd_dma_chan6: dma@ffad0000 {
 536                         status = "disabled";
 537                         compatible = "xlnx,zynqmp-dma-1.0";
 538                         reg = <0x0 0xffad0000 0x0 0x1000>;
 539                         interrupt-parent = <&gic>;
 540                         interrupts = <0 82 4>;
 541                         clock-names = "clk_main", "clk_apb";
 542                         xlnx,bus-width = <64>;
 543                         #stream-id-cells = <1>;
 544                         /* iommus = <&smmu 0x86d>; */
 545                         power-domains = <&zynqmp_firmware PD_ADMA>;
 546                 };
 547
 548                 lpd_dma_chan7: dma@ffae0000 {
 549                         status = "disabled";
 550                         compatible = "xlnx,zynqmp-dma-1.0";
 551                         reg = <0x0 0xffae0000 0x0 0x1000>;
 552                         interrupt-parent = <&gic>;
 553                         interrupts = <0 83 4>;
 554                         clock-names = "clk_main", "clk_apb";
 555                         xlnx,bus-width = <64>;
 556                         #stream-id-cells = <1>;
 557                         /* iommus = <&smmu 0x86e>; */
 558                         power-domains = <&zynqmp_firmware PD_ADMA>;
 559                 };
 560
 561                 lpd_dma_chan8: dma@ffaf0000 {
 562                         status = "disabled";
 563                         compatible = "xlnx,zynqmp-dma-1.0";
 564                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 565                         interrupt-parent = <&gic>;
 566                         interrupts = <0 84 4>;
 567                         clock-names = "clk_main", "clk_apb";
 568                         xlnx,bus-width = <64>;
 569                         #stream-id-cells = <1>;
 570                         /* iommus = <&smmu 0x86f>; */
 571                         power-domains = <&zynqmp_firmware PD_ADMA>;
 572                 };
 573
 574                 mc: memory-controller@fd070000 {
 575                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 576                         reg = <0x0 0xfd070000 0x0 0x30000>;
 577                         interrupt-parent = <&gic>;
 578                         interrupts = <0 112 4>;
 579                 };
 580
 581                 nand0: nand@ff100000 {
 582                         compatible = "arasan,nfc-v3p10";
 583                         status = "disabled";
 584                         reg = <0x0 0xff100000 0x0 0x1000>;
 585                         clock-names = "clk_sys", "clk_flash";
 586                         interrupt-parent = <&gic>;
 587                         interrupts = <0 14 4>;
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         #stream-id-cells = <1>;
 591                         iommus = <&smmu 0x872>;
 592                         power-domains = <&zynqmp_firmware PD_NAND>;
 593                 };
 594
 595                 gem0: ethernet@ff0b0000 {
 596                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 597                         status = "disabled";
 598                         interrupt-parent = <&gic>;
 599                         interrupts = <0 57 4>, <0 57 4>;
 600                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 601                         clock-names = "pclk", "hclk", "tx_clk";
 602                         #address-cells = <1>;
 603                         #size-cells = <0>;
 604                         #stream-id-cells = <1>;
 605                         iommus = <&smmu 0x874>;
 606                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 607                 };
 608
 609                 gem1: ethernet@ff0c0000 {
 610                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 611                         status = "disabled";
 612                         interrupt-parent = <&gic>;
 613                         interrupts = <0 59 4>, <0 59 4>;
 614                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 615                         clock-names = "pclk", "hclk", "tx_clk";
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         #stream-id-cells = <1>;
 619                         iommus = <&smmu 0x875>;
 620                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 621                 };
 622
 623                 gem2: ethernet@ff0d0000 {
 624                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 625                         status = "disabled";
 626                         interrupt-parent = <&gic>;
 627                         interrupts = <0 61 4>, <0 61 4>;
 628                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 629                         clock-names = "pclk", "hclk", "tx_clk";
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                         #stream-id-cells = <1>;
 633                         iommus = <&smmu 0x876>;
 634                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 635                 };
 636
 637                 gem3: ethernet@ff0e0000 {
 638                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 639                         status = "disabled";
 640                         interrupt-parent = <&gic>;
 641                         interrupts = <0 63 4>, <0 63 4>;
 642                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 643                         clock-names = "pclk", "hclk", "tx_clk";
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         #stream-id-cells = <1>;
 647                         iommus = <&smmu 0x877>;
 648                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 649                 };
 650
 651                 gpio: gpio@ff0a0000 {
 652                         compatible = "xlnx,zynqmp-gpio-1.0";
 653                         status = "disabled";
 654                         #gpio-cells = <0x2>;
 655                         interrupt-parent = <&gic>;
 656                         interrupts = <0 16 4>;
 657                         interrupt-controller;
 658                         #interrupt-cells = <2>;
 659                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 660                         gpio-controller;
 661                         power-domains = <&zynqmp_firmware PD_GPIO>;
 662                 };
 663
 664                 i2c0: i2c@ff020000 {
 665                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 666                         status = "disabled";
 667                         interrupt-parent = <&gic>;
 668                         interrupts = <0 17 4>;
 669                         reg = <0x0 0xff020000 0x0 0x1000>;
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 673                 };
 674
 675                 i2c1: i2c@ff030000 {
 676                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 677                         status = "disabled";
 678                         interrupt-parent = <&gic>;
 679                         interrupts = <0 18 4>;
 680                         reg = <0x0 0xff030000 0x0 0x1000>;
 681                         #address-cells = <1>;
 682                         #size-cells = <0>;
 683                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 684                 };
 685
 686                 ocm: memory-controller@ff960000 {
 687                         compatible = "xlnx,zynqmp-ocmc-1.0";
 688                         reg = <0x0 0xff960000 0x0 0x1000>;
 689                         interrupt-parent = <&gic>;
 690                         interrupts = <0 10 4>;
 691                 };
 692
 693                 perf_monitor_ocm: perf-monitor@ffa00000 {
 694                         compatible = "xlnx,axi-perf-monitor";
 695                         reg = <0x0 0xffa00000 0x0 0x10000>;
 696                         interrupts = <0 25 4>;
 697                         interrupt-parent = <&gic>;
 698                         xlnx,enable-profile = <0>;
 699                         xlnx,enable-trace = <0>;
 700                         xlnx,num-monitor-slots = <1>;
 701                         xlnx,enable-event-count = <1>;
 702                         xlnx,enable-event-log = <1>;
 703                         xlnx,have-sampled-metric-cnt = <1>;
 704                         xlnx,num-of-counters = <8>;
 705                         xlnx,metric-count-width = <32>;
 706                         xlnx,metrics-sample-count-width = <32>;
 707                         xlnx,global-count-width = <32>;
 708                         xlnx,metric-count-scale = <1>;
 709                 };
 710
 711                 perf_monitor_ddr: perf-monitor@fd0b0000 {
 712                         compatible = "xlnx,axi-perf-monitor";
 713                         reg = <0x0 0xfd0b0000 0x0 0x10000>;
 714                         interrupts = <0 123 4>;
 715                         interrupt-parent = <&gic>;
 716                         xlnx,enable-profile = <0>;
 717                         xlnx,enable-trace = <0>;
 718                         xlnx,num-monitor-slots = <6>;
 719                         xlnx,enable-event-count = <1>;
 720                         xlnx,enable-event-log = <0>;
 721                         xlnx,have-sampled-metric-cnt = <1>;
 722                         xlnx,num-of-counters = <10>;
 723                         xlnx,metric-count-width = <32>;
 724                         xlnx,metrics-sample-count-width = <32>;
 725                         xlnx,global-count-width = <32>;
 726                         xlnx,metric-count-scale = <1>;
 727                 };
 728
 729                 perf_monitor_cci: perf-monitor@fd490000 {
 730                         compatible = "xlnx,axi-perf-monitor";
 731                         reg = <0x0 0xfd490000 0x0 0x10000>;
 732                         interrupts = <0 123 4>;
 733                         interrupt-parent = <&gic>;
 734                         xlnx,enable-profile = <0>;
 735                         xlnx,enable-trace = <0>;
 736                         xlnx,num-monitor-slots = <1>;
 737                         xlnx,enable-event-count = <1>;
 738                         xlnx,enable-event-log = <0>;
 739                         xlnx,have-sampled-metric-cnt = <1>;
 740                         xlnx,num-of-counters = <8>;
 741                         xlnx,metric-count-width = <32>;
 742                         xlnx,metrics-sample-count-width = <32>;
 743                         xlnx,global-count-width = <32>;
 744                         xlnx,metric-count-scale = <1>;
 745                 };
 746
 747                 perf_monitor_lpd: perf-monitor@ffa10000 {
 748                         compatible = "xlnx,axi-perf-monitor";
 749                         reg = <0x0 0xffa10000 0x0 0x10000>;
 750                         interrupts = <0 25 4>;
 751                         interrupt-parent = <&gic>;
 752                         xlnx,enable-profile = <0>;
 753                         xlnx,enable-trace = <0>;
 754                         xlnx,num-monitor-slots = <1>;
 755                         xlnx,enable-event-count = <1>;
 756                         xlnx,enable-event-log = <1>;
 757                         xlnx,have-sampled-metric-cnt = <1>;
 758                         xlnx,num-of-counters = <8>;
 759                         xlnx,metric-count-width = <32>;
 760                         xlnx,metrics-sample-count-width = <32>;
 761                         xlnx,global-count-width = <32>;
 762                         xlnx,metric-count-scale = <1>;
 763                 };
 764
 765                 pcie: pcie@fd0e0000 {
 766                         compatible = "xlnx,nwl-pcie-2.11";
 767                         status = "disabled";
 768                         #address-cells = <3>;
 769                         #size-cells = <2>;
 770                         #interrupt-cells = <1>;
 771                         msi-controller;
 772                         device_type = "pci";
 773                         interrupt-parent = <&gic>;
 774                         interrupts = <0 118 4>,
 775                                      <0 117 4>,
 776                                      <0 116 4>,
 777                                      <0 115 4>, /* MSI_1 [63...32] */
 778                                      <0 114 4>; /* MSI_0 [31...0] */
 779                         interrupt-names = "misc", "dummy", "intx",
 780                                           "msi1", "msi0";
 781                         msi-parent = <&pcie>;
 782                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 783                               <0x0 0xfd480000 0x0 0x1000>,
 784                               <0x80 0x00000000 0x0 0x1000000>;
 785                         reg-names = "breg", "pcireg", "cfg";
 786                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 787                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 788                         bus-range = <0x00 0xff>;
 789                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 790                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 791                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 792                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 793                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 794                         power-domains = <&zynqmp_firmware PD_PCIE>;
 795                         pcie_intc: legacy-interrupt-controller {
 796                                 interrupt-controller;
 797                                 #address-cells = <0>;
 798                                 #interrupt-cells = <1>;
 799                         };
 800                 };
 801
 802                 qspi: spi@ff0f0000 {
 803                         u-boot,dm-pre-reloc;
 804                         compatible = "xlnx,zynqmp-qspi-1.0";
 805                         status = "disabled";
 806                         clock-names = "ref_clk", "pclk";
 807                         interrupts = <0 15 4>;
 808                         interrupt-parent = <&gic>;
 809                         num-cs = <1>;
 810                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 811                               <0x0 0xc0000000 0x0 0x8000000>;
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         #stream-id-cells = <1>;
 815                         iommus = <&smmu 0x873>;
 816                         power-domains = <&zynqmp_firmware PD_QSPI>;
 817                 };
 818
 819                 rtc: rtc@ffa60000 {
 820                         compatible = "xlnx,zynqmp-rtc";
 821                         status = "disabled";
 822                         reg = <0x0 0xffa60000 0x0 0x100>;
 823                         interrupt-parent = <&gic>;
 824                         interrupts = <0 26 4>, <0 27 4>;
 825                         interrupt-names = "alarm", "sec";
 826                         calibration = <0x8000>;
 827                 };
 828
 829                 serdes: zynqmp_phy@fd400000 {
 830                         compatible = "xlnx,zynqmp-psgtr-v1.1";
 831                         status = "disabled";
 832                         reg = <0x0 0xfd400000 0x0 0x40000>,
 833                               <0x0 0xfd3d0000 0x0 0x1000>;
 834                         reg-names = "serdes", "siou";
 835                         nvmem-cells = <&soc_revision>;
 836                         nvmem-cell-names = "soc_revision";
 837                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
 838                                  <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 839                                  <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 840                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 841                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 842                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
 843                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
 844                                  <&zynqmp_reset ZYNQMP_RESET_DP>,
 845                                  <&zynqmp_reset ZYNQMP_RESET_GEM0>,
 846                                  <&zynqmp_reset ZYNQMP_RESET_GEM1>,
 847                                  <&zynqmp_reset ZYNQMP_RESET_GEM2>,
 848                                  <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 849                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 850                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 851                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 852                                       "gem1_rst", "gem2_rst", "gem3_rst";
 853                         lane0: lane0 {
 854                                 #phy-cells = <4>;
 855                         };
 856                         lane1: lane1 {
 857                                 #phy-cells = <4>;
 858                         };
 859                         lane2: lane2 {
 860                                 #phy-cells = <4>;
 861                         };
 862                         lane3: lane3 {
 863                                 #phy-cells = <4>;
 864                         };
 865                 };
 866
 867                 sata: ahci@fd0c0000 {
 868                         compatible = "ceva,ahci-1v84";
 869                         status = "disabled";
 870                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 871                         interrupt-parent = <&gic>;
 872                         interrupts = <0 133 4>;
 873                         power-domains = <&zynqmp_firmware PD_SATA>;
 874                         #stream-id-cells = <4>;
 875                         /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, */
 876                         /*       <&smmu 0x4c2>, <&smmu 0x4c3>; */
 877                         /* dma-coherent; */
 878                 };
 879
 880                 sdhci0: mmc@ff160000 {
 881                         u-boot,dm-pre-reloc;
 882                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 883                         status = "disabled";
 884                         interrupt-parent = <&gic>;
 885                         interrupts = <0 48 4>;
 886                         reg = <0x0 0xff160000 0x0 0x1000>;
 887                         clock-names = "clk_xin", "clk_ahb";
 888                         xlnx,device_id = <0>;
 889                         #stream-id-cells = <1>;
 890                         iommus = <&smmu 0x870>;
 891                         power-domains = <&zynqmp_firmware PD_SD_0>;
 892                         nvmem-cells = <&soc_revision>;
 893                         nvmem-cell-names = "soc_revision";
 894                 };
 895
 896                 sdhci1: mmc@ff170000 {
 897                         u-boot,dm-pre-reloc;
 898                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 899                         status = "disabled";
 900                         interrupt-parent = <&gic>;
 901                         interrupts = <0 49 4>;
 902                         reg = <0x0 0xff170000 0x0 0x1000>;
 903                         clock-names = "clk_xin", "clk_ahb";
 904                         xlnx,device_id = <1>;
 905                         #stream-id-cells = <1>;
 906                         iommus = <&smmu 0x871>;
 907                         power-domains = <&zynqmp_firmware PD_SD_1>;
 908                         nvmem-cells = <&soc_revision>;
 909                         nvmem-cell-names = "soc_revision";
 910                 };
 911
 912                 spi0: spi@ff040000 {
 913                         compatible = "cdns,spi-r1p6";
 914                         status = "disabled";
 915                         interrupt-parent = <&gic>;
 916                         interrupts = <0 19 4>;
 917                         reg = <0x0 0xff040000 0x0 0x1000>;
 918                         clock-names = "ref_clk", "pclk";
 919                         #address-cells = <1>;
 920                         #size-cells = <0>;
 921                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 922                 };
 923
 924                 spi1: spi@ff050000 {
 925                         compatible = "cdns,spi-r1p6";
 926                         status = "disabled";
 927                         interrupt-parent = <&gic>;
 928                         interrupts = <0 20 4>;
 929                         reg = <0x0 0xff050000 0x0 0x1000>;
 930                         clock-names = "ref_clk", "pclk";
 931                         #address-cells = <1>;
 932                         #size-cells = <0>;
 933                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 934                 };
 935
 936                 ttc0: timer@ff110000 {
 937                         compatible = "cdns,ttc";
 938                         status = "disabled";
 939                         interrupt-parent = <&gic>;
 940                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 941                         reg = <0x0 0xff110000 0x0 0x1000>;
 942                         timer-width = <32>;
 943                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 944                 };
 945
 946                 ttc1: timer@ff120000 {
 947                         compatible = "cdns,ttc";
 948                         status = "disabled";
 949                         interrupt-parent = <&gic>;
 950                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 951                         reg = <0x0 0xff120000 0x0 0x1000>;
 952                         timer-width = <32>;
 953                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 954                 };
 955
 956                 ttc2: timer@ff130000 {
 957                         compatible = "cdns,ttc";
 958                         status = "disabled";
 959                         interrupt-parent = <&gic>;
 960                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 961                         reg = <0x0 0xff130000 0x0 0x1000>;
 962                         timer-width = <32>;
 963                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 964                 };
 965
 966                 ttc3: timer@ff140000 {
 967                         compatible = "cdns,ttc";
 968                         status = "disabled";
 969                         interrupt-parent = <&gic>;
 970                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 971                         reg = <0x0 0xff140000 0x0 0x1000>;
 972                         timer-width = <32>;
 973                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 974                 };
 975
 976                 uart0: serial@ff000000 {
 977                         u-boot,dm-pre-reloc;
 978                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 979                         status = "disabled";
 980                         interrupt-parent = <&gic>;
 981                         interrupts = <0 21 4>;
 982                         reg = <0x0 0xff000000 0x0 0x1000>;
 983                         clock-names = "uart_clk", "pclk";
 984                         power-domains = <&zynqmp_firmware PD_UART_0>;
 985                 };
 986
 987                 uart1: serial@ff010000 {
 988                         u-boot,dm-pre-reloc;
 989                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 990                         status = "disabled";
 991                         interrupt-parent = <&gic>;
 992                         interrupts = <0 22 4>;
 993                         reg = <0x0 0xff010000 0x0 0x1000>;
 994                         clock-names = "uart_clk", "pclk";
 995                         power-domains = <&zynqmp_firmware PD_UART_1>;
 996                 };
 997
 998                 usb0: usb0@ff9d0000 {
 999                         #address-cells = <2>;
1000                         #size-cells = <2>;
1001                         status = "disabled";
1002                         compatible = "xlnx,zynqmp-dwc3";
1003                         reg = <0x0 0xff9d0000 0x0 0x100>;
1004                         clock-names = "bus_clk", "ref_clk";
1005                         power-domains = <&zynqmp_firmware PD_USB_0>;
1006                         ranges;
1007                         nvmem-cells = <&soc_revision>;
1008                         nvmem-cell-names = "soc_revision";
1009
1010                         dwc3_0: dwc3@fe200000 {
1011                                 compatible = "snps,dwc3";
1012                                 status = "disabled";
1013                                 reg = <0x0 0xfe200000 0x0 0x40000>;
1014                                 interrupt-parent = <&gic>;
1015                                 interrupt-names = "dwc_usb3", "otg", "hiber";
1016                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
1017                                 #stream-id-cells = <1>;
1018                                 iommus = <&smmu 0x860>;
1019                                 snps,quirk-frame-length-adjustment = <0x20>;
1020                                 snps,refclk_fladj;
1021                                 snps,enable_guctl1_resume_quirk;
1022                                 snps,enable_guctl1_ipd_quirk;
1023                                 snps,xhci-stream-quirk;
1024                                 /* dma-coherent; */
1025                                 /* snps,enable-hibernation; */
1026                         };
1027                 };
1028
1029                 usb1: usb1@ff9e0000 {
1030                         #address-cells = <2>;
1031                         #size-cells = <2>;
1032                         status = "disabled";
1033                         compatible = "xlnx,zynqmp-dwc3";
1034                         reg = <0x0 0xff9e0000 0x0 0x100>;
1035                         clock-names = "bus_clk", "ref_clk";
1036                         power-domains = <&zynqmp_firmware PD_USB_1>;
1037                         ranges;
1038                         nvmem-cells = <&soc_revision>;
1039                         nvmem-cell-names = "soc_revision";
1040
1041                         dwc3_1: dwc3@fe300000 {
1042                                 compatible = "snps,dwc3";
1043                                 status = "disabled";
1044                                 reg = <0x0 0xfe300000 0x0 0x40000>;
1045                                 interrupt-parent = <&gic>;
1046                                 interrupt-names = "dwc_usb3", "otg", "hiber";
1047                                 interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
1048                                 #stream-id-cells = <1>;
1049                                 iommus = <&smmu 0x861>;
1050                                 snps,quirk-frame-length-adjustment = <0x20>;
1051                                 snps,refclk_fladj;
1052                                 snps,enable_guctl1_resume_quirk;
1053                                 snps,enable_guctl1_ipd_quirk;
1054                                 snps,xhci-stream-quirk;
1055                                 /* dma-coherent; */
1056                         };
1057                 };
1058
1059                 watchdog0: watchdog@fd4d0000 {
1060                         compatible = "cdns,wdt-r1p2";
1061                         status = "disabled";
1062                         interrupt-parent = <&gic>;
1063                         interrupts = <0 113 1>;
1064                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1065                         timeout-sec = <60>;
1066                         reset-on-timeout;
1067                 };
1068
1069                 lpd_watchdog: watchdog@ff150000 {
1070                         compatible = "cdns,wdt-r1p2";
1071                         status = "disabled";
1072                         interrupt-parent = <&gic>;
1073                         interrupts = <0 52 1>;
1074                         reg = <0x0 0xff150000 0x0 0x1000>;
1075                         timeout-sec = <10>;
1076                 };
1077
1078                 xilinx_ams: ams@ffa50000 {
1079                         compatible = "xlnx,zynqmp-ams";
1080                         status = "disabled";
1081                         interrupt-parent = <&gic>;
1082                         interrupts = <0 56 4>;
1083                         interrupt-names = "ams-irq";
1084                         reg = <0x0 0xffa50000 0x0 0x800>;
1085                         reg-names = "ams-base";
1086                         #address-cells = <2>;
1087                         #size-cells = <2>;
1088                         #io-channel-cells = <1>;
1089                         ranges;
1090
1091                         ams_ps: ams_ps@ffa50800 {
1092                                 compatible = "xlnx,zynqmp-ams-ps";
1093                                 status = "disabled";
1094                                 reg = <0x0 0xffa50800 0x0 0x400>;
1095                         };
1096
1097                         ams_pl: ams_pl@ffa50c00 {
1098                                 compatible = "xlnx,zynqmp-ams-pl";
1099                                 status = "disabled";
1100                                 reg = <0x0 0xffa50c00 0x0 0x400>;
1101                         };
1102                 };
1103
1104                 xlnx_dpdma: dma@fd4c0000 {
1105                         compatible = "xlnx,dpdma";
1106                         status = "disabled";
1107                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1108                         interrupts = <0 122 4>;
1109                         interrupt-parent = <&gic>;
1110                         clock-names = "axi_clk";
1111                         power-domains = <&zynqmp_firmware PD_DP>;
1112                         dma-channels = <6>;
1113                         #dma-cells = <1>;
1114                         dma-video0channel {
1115                                 compatible = "xlnx,video0";
1116                         };
1117                         dma-video1channel {
1118                                 compatible = "xlnx,video1";
1119                         };
1120                         dma-video2channel {
1121                                 compatible = "xlnx,video2";
1122                         };
1123                         dma-graphicschannel {
1124                                 compatible = "xlnx,graphics";
1125                         };
1126                         dma-audio0channel {
1127                                 compatible = "xlnx,audio0";
1128                         };
1129                         dma-audio1channel {
1130                                 compatible = "xlnx,audio1";
1131                         };
1132                 };
1133
1134                 zynqmp_dpsub: zynqmp-display@fd4a0000 {
1135                         compatible = "xlnx,zynqmp-dpsub-1.7";
1136                         status = "disabled";
1137                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
1138                               <0x0 0xfd4aa000 0x0 0x1000>,
1139                               <0x0 0xfd4ab000 0x0 0x1000>,
1140                               <0x0 0xfd4ac000 0x0 0x1000>;
1141                         reg-names = "dp", "blend", "av_buf", "aud";
1142                         interrupts = <0 119 4>;
1143                         interrupt-parent = <&gic>;
1144
1145                         clock-names = "dp_apb_clk", "dp_aud_clk",
1146                                       "dp_vtc_pixel_clk_in";
1147
1148                         power-domains = <&zynqmp_firmware PD_DP>;
1149
1150                         vid-layer {
1151                                 dma-names = "vid0", "vid1", "vid2";
1152                                 dmas = <&xlnx_dpdma 0>,
1153                                        <&xlnx_dpdma 1>,
1154                                        <&xlnx_dpdma 2>;
1155                         };
1156
1157                         gfx-layer {
1158                                 dma-names = "gfx0";
1159                                 dmas = <&xlnx_dpdma 3>;
1160                         };
1161
1162                         /* dummy node to indicate there's no child i2c device */
1163                         i2c-bus {
1164                         };
1165
1166                         zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
1167                                 compatible = "xlnx,dp-snd-codec";
1168                                 clock-names = "aud_clk";
1169                         };
1170
1171                         zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
1172                                 compatible = "xlnx,dp-snd-pcm";
1173                                 dmas = <&xlnx_dpdma 4>;
1174                                 dma-names = "tx";
1175                         };
1176
1177                         zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
1178                                 compatible = "xlnx,dp-snd-pcm";
1179                                 dmas = <&xlnx_dpdma 5>;
1180                                 dma-names = "tx";
1181                         };
1182
1183                         zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
1184                                 compatible = "xlnx,dp-snd-card";
1185                                 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
1186                                                   <&zynqmp_dp_snd_pcm1>;
1187                                 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
1188                         };
1189                 };
1190         };
1191 };