arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/phy/phy.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17
  18 / {
  19         model = "ZynqMP zc1751-xm015-dc1 RevA";
  20         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c1;
  26                 mmc0 = &sdhci0;
  27                 mmc1 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 spi0 = &qspi;
  31                 usb0 = &usb0;
  32         };
  33
  34         chosen {
  35                 bootargs = "earlycon";
  36                 stdout-path = "serial0:115200n8";
  37         };
  38
  39         memory@0 {
  40                 device_type = "memory";
  41                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  42         };
  43 };
  44
  45 &fpd_dma_chan1 {
  46         status = "okay";
  47 };
  48
  49 &fpd_dma_chan2 {
  50         status = "okay";
  51 };
  52
  53 &fpd_dma_chan3 {
  54         status = "okay";
  55 };
  56
  57 &fpd_dma_chan4 {
  58         status = "okay";
  59 };
  60
  61 &fpd_dma_chan5 {
  62         status = "okay";
  63 };
  64
  65 &fpd_dma_chan6 {
  66         status = "okay";
  67 };
  68
  69 &fpd_dma_chan7 {
  70         status = "okay";
  71 };
  72
  73 &fpd_dma_chan8 {
  74         status = "okay";
  75 };
  76
  77 &gem3 {
  78         status = "okay";
  79         phy-handle = <&phy0>;
  80         phy-mode = "rgmii-id";
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_gem3_default>;
  83         phy0: phy@0 {
  84                 reg = <0>;
  85         };
  86 };
  87
  88 &gpio {
  89         status = "okay";
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_gpio_default>;
  92 };
  93
  94 &gpu {
  95         status = "okay";
  96 };
  97
  98 &i2c1 {
  99         status = "okay";
 100         clock-frequency = <400000>;
 101         pinctrl-names = "default", "gpio";
 102         pinctrl-0 = <&pinctrl_i2c1_default>;
 103         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 104         scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
 105         sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
 106
 107         eeprom: eeprom@55 {
 108                 compatible = "atmel,24c64"; /* 24AA64 */
 109                 reg = <0x55>;
 110         };
 111 };
 112
 113 &pinctrl0 {
 114         status = "okay";
 115         pinctrl_i2c1_default: i2c1-default {
 116                 mux {
 117                         groups = "i2c1_9_grp";
 118                         function = "i2c1";
 119                 };
 120
 121                 conf {
 122                         groups = "i2c1_9_grp";
 123                         bias-pull-up;
 124                         slew-rate = <SLEW_RATE_SLOW>;
 125                         io-standard = <IO_STANDARD_LVCMOS18>;
 126                 };
 127         };
 128
 129         pinctrl_i2c1_gpio: i2c1-gpio {
 130                 mux {
 131                         groups = "gpio0_36_grp", "gpio0_37_grp";
 132                         function = "gpio0";
 133                 };
 134
 135                 conf {
 136                         groups = "gpio0_36_grp", "gpio0_37_grp";
 137                         slew-rate = <SLEW_RATE_SLOW>;
 138                         io-standard = <IO_STANDARD_LVCMOS18>;
 139                 };
 140         };
 141
 142         pinctrl_uart0_default: uart0-default {
 143                 mux {
 144                         groups = "uart0_8_grp";
 145                         function = "uart0";
 146                 };
 147
 148                 conf {
 149                         groups = "uart0_8_grp";
 150                         slew-rate = <SLEW_RATE_SLOW>;
 151                         io-standard = <IO_STANDARD_LVCMOS18>;
 152                 };
 153
 154                 conf-rx {
 155                         pins = "MIO34";
 156                         bias-high-impedance;
 157                 };
 158
 159                 conf-tx {
 160                         pins = "MIO35";
 161                         bias-disable;
 162                 };
 163         };
 164
 165         pinctrl_usb0_default: usb0-default {
 166                 mux {
 167                         groups = "usb0_0_grp";
 168                         function = "usb0";
 169                 };
 170
 171                 conf {
 172                         groups = "usb0_0_grp";
 173                         slew-rate = <SLEW_RATE_SLOW>;
 174                         io-standard = <IO_STANDARD_LVCMOS18>;
 175                 };
 176
 177                 conf-rx {
 178                         pins = "MIO52", "MIO53", "MIO55";
 179                         bias-high-impedance;
 180                 };
 181
 182                 conf-tx {
 183                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 184                                "MIO60", "MIO61", "MIO62", "MIO63";
 185                         bias-disable;
 186                 };
 187         };
 188
 189         pinctrl_gem3_default: gem3-default {
 190                 mux {
 191                         function = "ethernet3";
 192                         groups = "ethernet3_0_grp";
 193                 };
 194
 195                 conf {
 196                         groups = "ethernet3_0_grp";
 197                         slew-rate = <SLEW_RATE_SLOW>;
 198                         io-standard = <IO_STANDARD_LVCMOS18>;
 199                 };
 200
 201                 conf-rx {
 202                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 203                                                                         "MIO75";
 204                         bias-high-impedance;
 205                         low-power-disable;
 206                 };
 207
 208                 conf-tx {
 209                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 210                                                                         "MIO69";
 211                         bias-disable;
 212                         low-power-enable;
 213                 };
 214
 215                 mux-mdio {
 216                         function = "mdio3";
 217                         groups = "mdio3_0_grp";
 218                 };
 219
 220                 conf-mdio {
 221                         groups = "mdio3_0_grp";
 222                         slew-rate = <SLEW_RATE_SLOW>;
 223                         io-standard = <IO_STANDARD_LVCMOS18>;
 224                         bias-disable;
 225                 };
 226         };
 227
 228         pinctrl_sdhci0_default: sdhci0-default {
 229                 mux {
 230                         groups = "sdio0_0_grp";
 231                         function = "sdio0";
 232                 };
 233
 234                 conf {
 235                         groups = "sdio0_0_grp";
 236                         slew-rate = <SLEW_RATE_SLOW>;
 237                         io-standard = <IO_STANDARD_LVCMOS18>;
 238                         bias-disable;
 239                 };
 240
 241                 mux-cd {
 242                         groups = "sdio0_cd_0_grp";
 243                         function = "sdio0_cd";
 244                 };
 245
 246                 conf-cd {
 247                         groups = "sdio0_cd_0_grp";
 248                         bias-high-impedance;
 249                         bias-pull-up;
 250                         slew-rate = <SLEW_RATE_SLOW>;
 251                         io-standard = <IO_STANDARD_LVCMOS18>;
 252                 };
 253
 254                 mux-wp {
 255                         groups = "sdio0_wp_0_grp";
 256                         function = "sdio0_wp";
 257                 };
 258
 259                 conf-wp {
 260                         groups = "sdio0_wp_0_grp";
 261                         bias-high-impedance;
 262                         bias-pull-up;
 263                         slew-rate = <SLEW_RATE_SLOW>;
 264                         io-standard = <IO_STANDARD_LVCMOS18>;
 265                 };
 266         };
 267
 268         pinctrl_sdhci1_default: sdhci1-default {
 269                 mux {
 270                         groups = "sdio1_0_grp";
 271                         function = "sdio1";
 272                 };
 273
 274                 conf {
 275                         groups = "sdio1_0_grp";
 276                         slew-rate = <SLEW_RATE_SLOW>;
 277                         io-standard = <IO_STANDARD_LVCMOS18>;
 278                         bias-disable;
 279                 };
 280
 281                 mux-cd {
 282                         groups = "sdio1_cd_0_grp";
 283                         function = "sdio1_cd";
 284                 };
 285
 286                 conf-cd {
 287                         groups = "sdio1_cd_0_grp";
 288                         bias-high-impedance;
 289                         bias-pull-up;
 290                         slew-rate = <SLEW_RATE_SLOW>;
 291                         io-standard = <IO_STANDARD_LVCMOS18>;
 292                 };
 293
 294                 mux-wp {
 295                         groups = "sdio1_wp_0_grp";
 296                         function = "sdio1_wp";
 297                 };
 298
 299                 conf-wp {
 300                         groups = "sdio1_wp_0_grp";
 301                         bias-high-impedance;
 302                         bias-pull-up;
 303                         slew-rate = <SLEW_RATE_SLOW>;
 304                         io-standard = <IO_STANDARD_LVCMOS18>;
 305                 };
 306         };
 307
 308         pinctrl_gpio_default: gpio-default {
 309                 mux {
 310                         function = "gpio0";
 311                         groups = "gpio0_38_grp";
 312                 };
 313
 314                 conf {
 315                         groups = "gpio0_38_grp";
 316                         bias-disable;
 317                         slew-rate = <SLEW_RATE_SLOW>;
 318                         io-standard = <IO_STANDARD_LVCMOS18>;
 319                 };
 320         };
 321 };
 322
 323 &qspi {
 324         status = "okay";
 325         flash@0 {
 326                 compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */
 327                 #address-cells = <1>;
 328                 #size-cells = <1>;
 329                 reg = <0x0>;
 330                 spi-tx-bus-width = <1>;
 331                 spi-rx-bus-width = <4>;
 332                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 333                 partition@qspi-fsbl-uboot { /* for testing purpose */
 334                         label = "qspi-fsbl-uboot";
 335                         reg = <0x0 0x100000>;
 336                 };
 337                 partition@qspi-linux { /* for testing purpose */
 338                         label = "qspi-linux";
 339                         reg = <0x100000 0x500000>;
 340                 };
 341                 partition@qspi-device-tree { /* for testing purpose */
 342                         label = "qspi-device-tree";
 343                         reg = <0x600000 0x20000>;
 344                 };
 345                 partition@qspi-rootfs { /* for testing purpose */
 346                         label = "qspi-rootfs";
 347                         reg = <0x620000 0x5E0000>;
 348                 };
 349         };
 350 };
 351
 352 &rtc {
 353         status = "okay";
 354 };
 355
 356 &sata {
 357         status = "okay";
 358         /* SATA phy OOB timing settings */
 359         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 360         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 361         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 362         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 363         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 364         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 365         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 366         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 367         phy-names = "sata-phy";
 368         phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;
 369 };
 370
 371 /* eMMC */
 372 &sdhci0 {
 373         status = "okay";
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_sdhci0_default>;
 376         bus-width = <8>;
 377         xlnx,mio_bank = <0>;
 378 };
 379
 380 /* SD1 with level shifter */
 381 &sdhci1 {
 382         status = "okay";
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_sdhci1_default>;
 385         xlnx,mio_bank = <1>;
 386 };
 387
 388 &serdes {
 389         status = "okay";
 390 };
 391
 392 &uart0 {
 393         status = "okay";
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_uart0_default>;
 396 };
 397
 398 /* ULPI SMSC USB3320 */
 399 &usb0 {
 400         status = "okay";
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_usb0_default>;
 403 };
 404
 405 &dwc3_0 {
 406         status = "okay";
 407         dr_mode = "host";
 408         snps,usb3_lpm_capable;
 409         phy-names = "usb3-phy";
 410         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 411 };
 412
 413 &zynqmp_dpsub {
 414         status = "okay";
 415         phy-names = "dp-phy0", "dp-phy1";
 416         phys = <&lane1 PHY_TYPE_DP 0 0 27000000>,
 417                <&lane0 PHY_TYPE_DP 1 1 27000000>;
 418 };
 419
 420 &zynqmp_dp_snd_pcm0 {
 421         status = "okay";
 422 };
 423
 424 &zynqmp_dp_snd_pcm1 {
 425         status = "okay";
 426 };
 427
 428 &zynqmp_dp_snd_card0 {
 429         status = "okay";
 430 };
 431
 432 &zynqmp_dp_snd_codec0 {
 433         status = "okay";
 434 };
 435
 436 &xlnx_dpdma {
 437         status = "okay";
 438 };