drm: sdi: xilinx: correcting multi link payload value

Channel bit have to be set only in case of multi link data.
In SDI-TX logicore IP, except 3GB mode all other modes are
single link only, hence these bit is redundant.
3GB mode is dual link.
For 3GB mode first link have to be programmed as channel 1,
and second link payload have to be programmed as channel 3.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c b/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c
index d56e94c776413c15e396b680510d34b565a4fa49..5b0c429fd279977f4f159255ab32df896e2a43cb 100644 (file)
--- a/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c
+++ b/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c
@@ -978,9 +978,11 @@ static void xilinx_sdi_mode_set(struct drm_encoder *encoder,
        payload = xilinx_sdi_calc_st352_payld(sdi, adjusted_mode);
        dev_dbg(sdi->dev, "payload : %0x\n", payload);
 
-       for (i = 0; i < sdi->sdi_data_strm_prop_val / 2; i++)
-               xilinx_sdi_set_payload_data(sdi, i, payload |
-                                           (i << XSDI_CH_SHIFT));
+       for (i = 0; i < sdi->sdi_data_strm_prop_val / 2; i++) {
+               if (sdi->sdi_mod_prop_val == XSDI_MODE_3GB)
+                       payload |= (i << 1) << XSDI_CH_SHIFT;
+               xilinx_sdi_set_payload_data(sdi, i, payload);
+       }
 
        /* UHDSDI is fixed 2 pixels per clock, horizontal timings div by 2 */
        vm.hactive = adjusted_mode->hdisplay / PIXELS_PER_CLK;