From 6f6aa295259f402925b96a4388542d4c88517368 Mon Sep 17 00:00:00 2001 From: Saurabh Sengar Date: Tue, 29 Aug 2017 12:02:57 +0530 Subject: [PATCH] drm: sdi: xilinx: correcting multi link payload value Channel bit have to be set only in case of multi link data. In SDI-TX logicore IP, except 3GB mode all other modes are single link only, hence these bit is redundant. 3GB mode is dual link. For 3GB mode first link have to be programmed as channel 1, and second link payload have to be programmed as channel 3. Signed-off-by: Saurabh Sengar Reviewed-by: Hyun Kwon Signed-off-by: Michal Simek --- drivers/gpu/drm/xilinx/xilinx_drm_sdi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c b/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c index d56e94c77641..5b0c429fd279 100644 --- a/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c +++ b/drivers/gpu/drm/xilinx/xilinx_drm_sdi.c @@ -978,9 +978,11 @@ static void xilinx_sdi_mode_set(struct drm_encoder *encoder, payload = xilinx_sdi_calc_st352_payld(sdi, adjusted_mode); dev_dbg(sdi->dev, "payload : %0x\n", payload); - for (i = 0; i < sdi->sdi_data_strm_prop_val / 2; i++) - xilinx_sdi_set_payload_data(sdi, i, payload | - (i << XSDI_CH_SHIFT)); + for (i = 0; i < sdi->sdi_data_strm_prop_val / 2; i++) { + if (sdi->sdi_mod_prop_val == XSDI_MODE_3GB) + payload |= (i << 1) << XSDI_CH_SHIFT; + xilinx_sdi_set_payload_data(sdi, i, payload); + } /* UHDSDI is fixed 2 pixels per clock, horizontal timings div by 2 */ vm.hactive = adjusted_mode->hdisplay / PIXELS_PER_CLK; -- 2.39.2