]> rtime.felk.cvut.cz Git - vajnamar/linux-xlnx.git/commitdiff
can: xilinx: proper acknowledgment of ISR Flags.
authorMousumi Jana <mousumi.jana@xilinx.com>
Thu, 12 Oct 2017 11:33:11 +0000 (17:03 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 17 Oct 2017 09:01:38 +0000 (11:01 +0200)
This patch adds the correct acknowledgment of the
ISR Flags. Previously all the bitflags are used to
acknowledge all kind of interrupts.But now required
flags are acknowledged.

Signed-off-by: Mousumi Jana <mousumij@xilinx.com>
Reviewed-by: Kedareswara Rao appana<appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/net/can/xilinx_can.c

index f238670889824010d0d397c3cbdac828b5ff8fe2..d0323da4c0740dc48f3118da64c33976aecd0955 100644 (file)
@@ -1129,8 +1129,10 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id)
 
        /* Check for the type of interrupt and Processing it */
        if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
-               priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
-                               XCAN_IXR_WKUP_MASK));
+               if (isr & XCAN_IXR_SLP_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_SLP_MASK);
+               if (isr & XCAN_IXR_WKUP_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_WKUP_MASK);
                xcan_state_interrupt(ndev, isr);
        }
 
@@ -1141,9 +1143,15 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id)
        /* Check for the type of error interrupt and Processing it */
        if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
                        XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
-               priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
-                               XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
-                               XCAN_IXR_ARBLST_MASK));
+               if (isr & XCAN_IXR_ERROR_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_ERROR_MASK);
+               if (isr & XCAN_IXR_RXOFLW_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOFLW_MASK);
+               if (isr & XCAN_IXR_BSOFF_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_BSOFF_MASK);
+               if (isr & XCAN_IXR_ARBLST_MASK)
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_ARBLST_MASK);
+
                xcan_err_interrupt(ndev, isr);
        }
        if (priv->quirks & CANFD_SUPPORT) {