ARM: tegra: pmc: T12x wake status clear fix

Problem:
 T12x PMC Wake status gets cleared during
 LP0 resume

Cause:
 During LP0 resume, T12x APBDEV_PMC_DPD_ENABLE_0
 register's TSC_MULT_EN bit needs to be
 programmed after DPD_ENABLE is cleared.

Fix:
 Cleared the DPD_ENABLE bit along with
 TSC_MULT_EN bit clear during LP0 resume
 for T12x

bug 1367291

Change-Id: Ifcc25709ffb012b4e6d4d0bb325f12d1ede94413
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/273646
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 96770dc17fe7bf89f7f59d2371061c6e67fa577c..786d74c41c6e93bac4e0b5d142600d09da5fc56c 100644 (file)
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -2027,6 +2027,9 @@ static u32 tsc_resume_start;
 
 #define PMC_DPD_ENABLE                 0x24
 #define PMC_DPD_ENABLE_TSC_MULT_ENABLE (1 << 1)
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#define PMC_DPD_ENABLE_ON              (1 << 0)
+#endif
 
 #define PMC_TSC_MULT                   0x2b4
 #define PMC_TSC_MULT_FREQ_STS          (1 << 16)
@@ -2050,6 +2053,14 @@ void tegra_tsc_resume(void)
                u32 reg = pmc_readl(PMC_DPD_ENABLE);
                BUG_ON(!(reg & PMC_DPD_ENABLE_TSC_MULT_ENABLE));
                reg &= ~PMC_DPD_ENABLE_TSC_MULT_ENABLE;
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
+               /*
+                * FIXME: T12x SW WAR -
+                * Resume ensures DPD_ENABLE is 0 when writing
+                * TSC_MULT_ENABLE, else PMC wake status gets reset
+                */
+               reg &= ~PMC_DPD_ENABLE_ON;
+#endif
                pmc_writel(reg, PMC_DPD_ENABLE);
                tsc_resume_start = timer_readl(TIMERUS_CNTR_1US);
        }