struct tegra_dsi_cmd *cmd, u8 delay_ms)
{
int err = 0;
+ int restore_err = 0;
struct dsi_status *init_status;
init_status = tegra_dsi_prepare_host_transmission(
}
err = _tegra_dsi_write_data(dsi, cmd);
- if (err < 0)
+ if (err < 0) {
dev_err(&dc->ndev->dev, "Failed DSI write\n");
+ restore_err = tegra_dsi_restore_state(dc, dsi, init_status);
+ if (restore_err < 0)
+ dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
+ goto fail;
+ }
mdelay(delay_ms);
u32 i;
int err;
u8 delay_ms;
+ int retry_count;
err = 0;
for (i = 0; i < n_cmd; i++) {
delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
i++;
}
- err = tegra_dsi_write_data_nosync(dc, dsi,
+ retry_count = DSI_WRITE_DATA_RETRY_ATTEMPTS;
+ do {
+ err = tegra_dsi_write_data_nosync(dc, dsi,
cur_cmd, delay_ms);
- if (err < 0)
- break;
+ if (err < 0) {
+ retry_count--;
+ dev_err(&dsi->dc->ndev->dev,
+ "dsi: %s failed, retrying...\n",__func__);
+ } else {
+ retry_count = 0;
+ }
+ } while (retry_count);
}
}
return err;
#define DSI_DELAY_FOR_READ_FIFO 5
+#define DSI_WRITE_DATA_RETRY_ATTEMPTS 5
+
/* Dsi virtual channel bit position, refer to the DSI specs */
#define DSI_VIR_CHANNEL_BIT_POSITION 6