drivers/video/tegra/dc/dsi.c

   1 /*
   2  * drivers/video/tegra/dc/dsi.c
   3  *
   4  * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/export.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/nvhost.h>
  32 #include <linux/lcm.h>
  33 #include <linux/gcd.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/clk/tegra.h>
  37 #include <linux/tegra-soc.h>
  38 #include <linux/nvhost.h>
  39 #include <linux/of_address.h>
  40
  41 #include <mach/dc.h>
  42 #include <mach/fb.h>
  43 #include <mach/csi.h>
  44 #include <mach/io_dpd.h>
  45
  46 #include "dc_reg.h"
  47 #include "dc_priv.h"
  48 #include "dev.h"
  49 #include "dsi_regs.h"
  50 #include "dsi.h"
  51 #include "mipi_cal.h"
  52 #include "of_dc.h"
  53
  54 /* HACK! This needs to come from DT */
  55 #include "../../../../arch/arm/mach-tegra/iomap.h"
  56
  57 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
  58 #define DSIB_MODE_ENABLE                0x2
  59
  60 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
  61         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
  62         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
  63         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
  64 #define DSI_USE_SYNC_POINTS 1
  65 #else
  66 #define DSI_USE_SYNC_POINTS 0
  67 #endif
  68
  69 #define S_TO_MS(x)                      (1000 * (x))
  70 #define MS_TO_US(x)                     (1000 * (x))
  71
  72 #define DSI_MODULE_NOT_INIT             0x0
  73 #define DSI_MODULE_INIT                 0x1
  74
  75 #define DSI_LPHS_NOT_INIT               0x0
  76 #define DSI_LPHS_IN_LP_MODE             0x1
  77 #define DSI_LPHS_IN_HS_MODE             0x2
  78
  79 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
  80 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
  81 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
  82
  83 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
  84 #define DSI_DRIVEN_MODE_DC              0x1
  85 #define DSI_DRIVEN_MODE_HOST            0x2
  86
  87 #define DSI_PHYCLK_OUT_DIS              0x0
  88 #define DSI_PHYCLK_OUT_EN               0x1
  89
  90 #define DSI_PHYCLK_NOT_INIT             0x0
  91 #define DSI_PHYCLK_CONTINUOUS           0x1
  92 #define DSI_PHYCLK_TX_ONLY              0x2
  93
  94 #define DSI_CLK_BURST_NOT_INIT          0x0
  95 #define DSI_CLK_BURST_NONE_BURST        0x1
  96 #define DSI_CLK_BURST_BURST_MODE        0x2
  97
  98 #define DSI_DC_STREAM_DISABLE           0x0
  99 #define DSI_DC_STREAM_ENABLE            0x1
 100
 101 #define DSI_LP_OP_NOT_INIT              0x0
 102 #define DSI_LP_OP_WRITE                 0x1
 103 #define DSI_LP_OP_READ                  0x2
 104
 105 #define DSI_HOST_IDLE_PERIOD            1000
 106 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
 107
 108 static bool enable_read_debug;
 109 module_param(enable_read_debug, bool, 0644);
 110 MODULE_PARM_DESC(enable_read_debug,
 111                 "Enable to print read fifo and return packet type");
 112
 113 static struct tegra_io_dpd dsi_io = {
 114         .name                   = "DSI",
 115         .io_dpd_reg_index       = 0,
 116         .io_dpd_bit             = 2,
 117 };
 118 static struct tegra_io_dpd dsib_io = {
 119         .name                   = "DSIB",
 120         .io_dpd_reg_index       = 1,
 121         .io_dpd_bit             = 7,
 122 };
 123 static struct tegra_io_dpd dsic_io = {
 124         .name                   = "DSIC",
 125         .io_dpd_reg_index       = 1,
 126         .io_dpd_bit             = 8,
 127 };
 128 static struct tegra_io_dpd dsid_io = {
 129         .name                   = "DSID",
 130         .io_dpd_reg_index       = 1,
 131         .io_dpd_bit             = 9,
 132 };
 133
 134 bool tegra_dsi_enable_read_debug(struct tegra_dc_dsi_data *dsi)
 135 {
 136         enable_read_debug = true;
 137         return enable_read_debug;
 138 }
 139
 140 bool tegra_dsi_disable_read_debug(struct tegra_dc_dsi_data *dsi)
 141 {
 142         enable_read_debug = false;
 143         return enable_read_debug;
 144 }
 145
 146 /* source of video data */
 147 enum {
 148         TEGRA_DSI_DRIVEN_BY_DC,
 149         TEGRA_DSI_DRIVEN_BY_HOST,
 150 };
 151
 152 static const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
 153         DSI_PKT_SEQ_0_LO,
 154         DSI_PKT_SEQ_0_HI,
 155         DSI_PKT_SEQ_1_LO,
 156         DSI_PKT_SEQ_1_HI,
 157         DSI_PKT_SEQ_2_LO,
 158         DSI_PKT_SEQ_2_HI,
 159         DSI_PKT_SEQ_3_LO,
 160         DSI_PKT_SEQ_3_HI,
 161         DSI_PKT_SEQ_4_LO,
 162         DSI_PKT_SEQ_4_HI,
 163         DSI_PKT_SEQ_5_LO,
 164         DSI_PKT_SEQ_5_HI,
 165 };
 166
 167 static const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
 168         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 169         0,
 170         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 171         0,
 172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 173         0,
 174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 175         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 176         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 177         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 179         0,
 180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 181         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 182         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 183         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 184 };
 185
 186 static const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
 187         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 188         0,
 189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 190         0,
 191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 192         0,
 193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 194         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 195         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 197         0,
 198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 199         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 200         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 201 };
 202
 203 static const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
 204         PKT_ID0(CMD_VS) | PKT_LEN0(0),
 205         0,
 206         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 207         0,
 208         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 209         0,
 210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 211         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 212         0,
 213         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 214         0,
 215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 216         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 217         0,
 218 };
 219
 220 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
 221         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 222         0,
 223         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 224         0,
 225         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 226         0,
 227         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 228         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 229         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 230         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 231         0,
 232         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 233         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 234         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 235 };
 236
 237 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
 238         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 239         0,
 240         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 241         0,
 242         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 243         0,
 244         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 245         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 246         0,
 247         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 248         0,
 249         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 250         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 251         0,
 252 };
 253
 254 static const u32 dsi_pkt_seq_video_non_burst_no_eot[NUMOF_PKT_SEQ] = {
 255         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 256         0,
 257         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 258         0,
 259         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 260         0,
 261         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 262                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 263         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 264         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 265         0,
 266         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 267                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 268         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 269 };
 270
 271 static const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         0,
 278         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 279                 PKT_LEN1(7) | PKT_LP,
 280         0,
 281         0,
 282         0,
 283         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) |
 284                 PKT_LEN1(7) | PKT_LP,
 285         0,
 286 };
 287
 288 static const u32 init_reg[] = {
 289         DSI_INT_ENABLE,
 290         DSI_INT_STATUS,
 291         DSI_INT_MASK,
 292         DSI_INIT_SEQ_DATA_0,
 293         DSI_INIT_SEQ_DATA_1,
 294         DSI_INIT_SEQ_DATA_2,
 295         DSI_INIT_SEQ_DATA_3,
 296         DSI_INIT_SEQ_DATA_4,
 297         DSI_INIT_SEQ_DATA_5,
 298         DSI_INIT_SEQ_DATA_6,
 299         DSI_INIT_SEQ_DATA_7,
 300         DSI_INIT_SEQ_DATA_15,
 301         DSI_DCS_CMDS,
 302         DSI_PKT_SEQ_0_LO,
 303         DSI_PKT_SEQ_1_LO,
 304         DSI_PKT_SEQ_2_LO,
 305         DSI_PKT_SEQ_3_LO,
 306         DSI_PKT_SEQ_4_LO,
 307         DSI_PKT_SEQ_5_LO,
 308         DSI_PKT_SEQ_0_HI,
 309         DSI_PKT_SEQ_1_HI,
 310         DSI_PKT_SEQ_2_HI,
 311         DSI_PKT_SEQ_3_HI,
 312         DSI_PKT_SEQ_4_HI,
 313         DSI_PKT_SEQ_5_HI,
 314         DSI_CONTROL,
 315         DSI_HOST_DSI_CONTROL,
 316         DSI_PAD_CONTROL,
 317         DSI_PAD_CONTROL_CD,
 318         DSI_SOL_DELAY,
 319         DSI_MAX_THRESHOLD,
 320         DSI_TRIGGER,
 321         DSI_TX_CRC,
 322         DSI_INIT_SEQ_CONTROL,
 323         DSI_PKT_LEN_0_1,
 324         DSI_PKT_LEN_2_3,
 325         DSI_PKT_LEN_4_5,
 326         DSI_PKT_LEN_6_7,
 327 };
 328
 329 static const u32 init_reg_vs1_ext[] = {
 330         DSI_PAD_CONTROL_0_VS1,
 331         DSI_PAD_CONTROL_CD_VS1,
 332         DSI_PAD_CD_STATUS_VS1,
 333         DSI_PAD_CONTROL_1_VS1,
 334         DSI_PAD_CONTROL_2_VS1,
 335         DSI_PAD_CONTROL_3_VS1,
 336         DSI_PAD_CONTROL_4_VS1,
 337         DSI_GANGED_MODE_CONTROL,
 338         DSI_GANGED_MODE_START,
 339         DSI_GANGED_MODE_SIZE,
 340 };
 341
 342 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
 343 static int tegra_dsi_host_resume(struct tegra_dc *dc);
 344 static void tegra_dc_dsi_idle_work(struct work_struct *work);
 345 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
 346                                      struct tegra_dc_dsi_data *dsi,
 347                                      int no_of_frames);
 348
 349 unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
 350                                                         u32 reg, int index)
 351 {
 352         unsigned long ret;
 353
 354         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 355         if (likely(tegra_platform_is_silicon())) {
 356                 if (WARN(!tegra_is_clk_enabled(dsi->dsi_clk[index]),
 357                 "DSI is clock gated!"))
 358                         return 0;
 359         }
 360         ret = readl(dsi->base[index] + reg * 4);
 361         trace_display_readl(dsi->dc, ret, dsi->base[index] + reg * 4);
 362         return ret;
 363 }
 364 EXPORT_SYMBOL(tegra_dsi_controller_readl);
 365
 366 void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
 367                                                 u32 val, u32 reg, int index)
 368 {
 369         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 370         if (likely(tegra_platform_is_silicon())) {
 371                 if (WARN(!tegra_is_clk_enabled(dsi->dsi_clk[index]),
 372                 "DSI is clock gated!"))
 373                         return;
 374         }
 375         trace_display_writel(dsi->dc, val, dsi->base[index] + reg * 4);
 376         writel(val, dsi->base[index] + reg * 4);
 377 }
 378 EXPORT_SYMBOL(tegra_dsi_controller_writel);
 379
 380 unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 381 {
 382         unsigned long ret;
 383         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 384         ret = readl(dsi->base[DSI_INSTANCE_0] + reg * 4);
 385         trace_display_readl(dsi->dc, ret, dsi->base[DSI_INSTANCE_0] + reg * 4);
 386         return ret;
 387 }
 388 EXPORT_SYMBOL(tegra_dsi_readl);
 389
 390 void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 391 {
 392         int  i = 0;
 393         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 394         for (i = 0; i < dsi->max_instances; i++) {
 395                 trace_display_writel(dsi->dc, val, dsi->base[i] + reg * 4);
 396                 writel(val, dsi->base[i] + reg * 4);
 397         }
 398 }
 399 EXPORT_SYMBOL(tegra_dsi_writel);
 400
 401 inline void tegra_dsi_reset_deassert(struct tegra_dc_dsi_data *dsi)
 402 {
 403         int i = 0;
 404         for (i = 0; i < dsi->max_instances; i++)
 405                 tegra_periph_reset_deassert(dsi->dsi_clk[i]);
 406 }
 407
 408 inline void tegra_dsi_reset_assert(struct tegra_dc_dsi_data *dsi)
 409 {
 410         int i = 0;
 411         for (i = 0; i < dsi->max_instances; i++)
 412                 tegra_periph_reset_assert(dsi->dsi_clk[i]);
 413 }
 414
 415 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi);
 416 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi);
 417
 418 void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
 419 {
 420         int i = 0;
 421         for (i = 0; i < dsi->max_instances; i++) {
 422                 clk_prepare_enable(dsi->dsi_clk[i]);
 423                 udelay(800);
 424         }
 425 }
 426
 427 void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
 428 {
 429         int i = 0;
 430         for (i = 0; i < dsi->max_instances; i++) {
 431                 clk_disable_unprepare(dsi->dsi_clk[i]);
 432                 udelay(800);
 433         }
 434 }
 435
 436 static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi)
 437 {
 438         int i = 0;
 439         for (i = 0; i < dsi->max_instances; i++) {
 440                 clk_prepare_enable(dsi->dsi_lp_clk[i]);
 441                 udelay(800);
 442         }
 443 }
 444
 445 static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi)
 446 {
 447         int i = 0;
 448         for (i = 0; i < dsi->max_instances; i++) {
 449                 clk_disable_unprepare(dsi->dsi_lp_clk[i]);
 450                 udelay(800);
 451         }
 452 }
 453
 454 static void tegra_dsi_setup_clk(struct tegra_dc *dc,
 455         struct tegra_dc_dsi_data *dsi)
 456 {
 457         int i = 0;
 458
 459         for (i = 0; i < dsi->max_instances; i++) {
 460                 tegra_dc_setup_clk(dc, dsi->dsi_clk[i]);
 461                 mdelay(3);
 462         }
 463 }
 464
 465 static void __maybe_unused tegra_dsi_syncpt_reset(
 466                                 struct tegra_dc_dsi_data *dsi)
 467 {
 468         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
 469         /* stabilization delay */
 470         udelay(300);
 471         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
 472         /* stabilization delay */
 473         udelay(300);
 474 }
 475
 476 static int __maybe_unused tegra_dsi_syncpt
 477         (struct tegra_dc_dsi_data *dsi, u8 link_id)
 478 {
 479         u32 val;
 480         int ret = 0;
 481
 482         if (!nvhost_syncpt_read_ext_check(dsi->dc->ndev, dsi->syncpt_id, &val))
 483                 dsi->syncpt_val = val;
 484
 485         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
 486                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
 487         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
 488                 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
 489         else
 490                 tegra_dsi_controller_writel(dsi, val, DSI_INCR_SYNCPT, link_id);
 491
 492         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
 493                 dsi->syncpt_val + 1, msecs_to_jiffies(500), NULL, NULL);
 494         if (ret < 0) {
 495                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
 496                 goto fail;
 497         }
 498
 499         (dsi->syncpt_val)++;
 500         return 0;
 501 fail:
 502         return ret;
 503 }
 504
 505 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
 506 {
 507         u32 dsi_clock_rate_khz;
 508
 509         switch (dsi->info.video_burst_mode) {
 510         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
 511         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
 512         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
 513         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
 514                 /* Calculate DSI HS clock rate for DSI burst mode */
 515                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
 516                                         dsi->shift_clk_div.mul /
 517                                         dsi->shift_clk_div.div;
 518                 break;
 519         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
 520         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
 521         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
 522         default:
 523                 /* Clock rate is default DSI clock rate for non-burst mode */
 524                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
 525                 break;
 526         }
 527
 528         return dsi_clock_rate_khz;
 529 }
 530
 531 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
 532 {
 533         u32 dsi_clock_rate_khz;
 534
 535         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 536                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
 537                         dsi_clock_rate_khz =
 538                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
 539                 else
 540                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
 541         else
 542                 if (lp_op == DSI_LP_OP_READ)
 543                         dsi_clock_rate_khz =
 544                                 dsi->info.lp_read_cmd_mode_freq_khz;
 545                 else
 546                         dsi_clock_rate_khz =
 547                                 dsi->info.lp_cmd_mode_freq_khz;
 548
 549         return dsi_clock_rate_khz;
 550 }
 551
 552 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
 553                                                 struct tegra_dc_dsi_data *dsi)
 554 {
 555         struct tegra_dc_shift_clk_div shift_clk_div;
 556         struct tegra_dc_shift_clk_div max_shift_clk_div;
 557         struct tegra_dc_shift_clk_div delta_shift_clk_div;
 558         u32 temp_lcm;
 559         u32 burst_width;
 560         u32 burst_width_max;
 561         u32 temp_gcd;
 562         u32 default_hs_clk_mhz =
 563                 DIV_ROUND_CLOSEST(dsi->default_hs_clk_khz, 1000);
 564         u32 max_panel_freq_mhz =
 565                 DIV_ROUND_CLOSEST(dsi->info.max_panel_freq_khz, 1000);
 566
 567         /* Get the real value of default shift_clk_div. default_shift_clk_div
 568          * holds the real value of shift_clk_div.
 569          */
 570         shift_clk_div = dsi->default_shift_clk_div;
 571
 572         /* Calculate shift_clk_div which can match the video_burst_mode. */
 573         if (dsi->info.video_burst_mode >=
 574                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
 575                 if (max_panel_freq_mhz >= default_hs_clk_mhz) {
 576                         /* formula:
 577                          * dsi->info.max_panel_freq_khz * shift_clk_div /
 578                          * dsi->default_hs_clk_khz
 579                          */
 580                         max_shift_clk_div.mul = max_panel_freq_mhz *
 581                                                 shift_clk_div.mul;
 582                         max_shift_clk_div.div = default_hs_clk_mhz *
 583                                                 shift_clk_div.div;
 584                 } else {
 585                         max_shift_clk_div = shift_clk_div;
 586                 }
 587
 588                 burst_width = dsi->info.video_burst_mode
 589                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 590                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
 591                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 592
 593                 /* formula:
 594                  * (max_shift_clk_div - shift_clk_div) *
 595                  * burst_width / burst_width_max
 596                  */
 597                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
 598                 delta_shift_clk_div.mul = (temp_lcm / max_shift_clk_div.div *
 599                                         max_shift_clk_div.mul -
 600                                         temp_lcm / shift_clk_div.div *
 601                                         shift_clk_div.mul) *
 602                                         burst_width;
 603                 delta_shift_clk_div.div = temp_lcm * burst_width_max;
 604
 605                 /* formula:
 606                  * shift_clk_div + delta_shift_clk_div
 607                  */
 608                 temp_lcm = lcm(shift_clk_div.div, delta_shift_clk_div.div);
 609                 shift_clk_div.mul = temp_lcm / shift_clk_div.div *
 610                                 shift_clk_div.mul +
 611                                 temp_lcm / delta_shift_clk_div.div *
 612                                 delta_shift_clk_div.mul;
 613                 shift_clk_div.div = temp_lcm;
 614
 615                 /* crunch shift clk numerator and denominator */
 616                 temp_gcd = gcd(shift_clk_div.mul, shift_clk_div.div);
 617                 shift_clk_div.mul /= temp_gcd;
 618                 shift_clk_div.div /= temp_gcd;
 619         }
 620
 621         return shift_clk_div;
 622 }
 623
 624 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
 625                                         struct tegra_dc_dsi_data *dsi)
 626 {
 627         u32 h_width_pixels;
 628         u32 h_act_corr = 0;
 629         u32 hfp_corr = 0;
 630         u32 temp = 0;
 631
 632         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 633                         dc->mode.h_sync_width + dc->mode.h_active;
 634
 635         if (WARN(!dsi->info.n_data_lanes, "dsi n_data_lanes is 0\n"))
 636                 return;
 637
 638         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
 639                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
 640                 if (temp) {
 641                         h_act_corr = dsi->info.n_data_lanes - temp;
 642                         h_width_pixels += h_act_corr;
 643                 }
 644         }
 645
 646         temp = h_width_pixels % dsi->info.n_data_lanes;
 647         if (temp) {
 648                 hfp_corr = dsi->info.n_data_lanes - temp;
 649                 h_width_pixels += hfp_corr;
 650         }
 651
 652         while (1) {
 653                 if (WARN(!dsi->pixel_scaler_div, "dsi pixel_scaler_div is 0"))
 654                         temp = 0;
 655                 else
 656                         temp = (h_width_pixels * dsi->pixel_scaler_mul /
 657                                 dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
 658                 if (temp) {
 659                         hfp_corr += dsi->info.n_data_lanes;
 660                         h_width_pixels += dsi->info.n_data_lanes;
 661                 } else
 662                         break;
 663         }
 664
 665         dc->mode.h_front_porch += hfp_corr;
 666         dc->mode.h_active += h_act_corr;
 667 }
 668
 669 void tegra_dsi_init_clock_param(struct tegra_dc *dc)
 670 {
 671         u32 h_width_pixels;
 672         u32 v_width_lines;
 673         u32 pixel_clk_hz;
 674         u32 byte_clk_hz;
 675         u32 plld_clk_mhz;
 676         u8 n_data_lanes;
 677
 678         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
 679
 680         switch (dsi->info.pixel_format) {
 681         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
 682                 /* 2 bytes per pixel */
 683                 dsi->pixel_scaler_mul = 2;
 684                 dsi->pixel_scaler_div = 1;
 685                 break;
 686         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
 687                 /* 2.25 bytes per pixel */
 688                 dsi->pixel_scaler_mul = 9;
 689                 dsi->pixel_scaler_div = 4;
 690                 break;
 691         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
 692         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
 693                 /* 3 bytes per pixel */
 694                 dsi->pixel_scaler_mul = 3;
 695                 dsi->pixel_scaler_div = 1;
 696                 break;
 697         default:
 698                 break;
 699         }
 700
 701         n_data_lanes = dsi->info.n_data_lanes;
 702         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
 703                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD ||
 704                 dsi->info.ganged_type ==
 705                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP)
 706                 n_data_lanes /= 2;
 707
 708         dsi->dsi_control_val =
 709                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
 710                         DSI_CONTROL_NUM_DATA_LANES(n_data_lanes - 1) |
 711                         DSI_CONTROL_VID_SOURCE(dc->ctrl_num) |
 712                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
 713
 714         if (dsi->info.ganged_type)
 715                 tegra_dsi_pix_correction(dc, dsi);
 716
 717         /* Below we are going to calculate dsi and dc clock rate.
 718          * Calcuate the horizontal and vertical width.
 719          */
 720         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 721                         dc->mode.h_sync_width + dc->mode.h_active;
 722
 723         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
 724                         dc->mode.v_sync_width + dc->mode.v_active;
 725
 726         /* Calculate minimum required pixel rate. */
 727         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
 728         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
 729                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
 730                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
 731                                 "should be larger than rated refresh rate.\n");
 732                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
 733                                                 dsi->info.rated_refresh_rate;
 734         }
 735
 736         /* Calculate minimum byte rate on DSI interface. */
 737         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
 738                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
 739
 740         /* Round up to multiple of mega hz. */
 741         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
 742                                                                 1000000);
 743
 744         /* Calculate default real shift_clk_div. */
 745         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
 746                                         dsi->pixel_scaler_mul;
 747         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
 748                                         dsi->info.n_data_lanes;
 749
 750
 751         /* Calculate default DSI hs clock. DSI interface is double data rate.
 752          * Data is transferred on both rising and falling edge of clk, div by 2
 753          * to get the actual clock rate.
 754          */
 755         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
 756
 757         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
 758                                         dsi->default_shift_clk_div.div) /
 759                                         (2 * dsi->default_shift_clk_div.mul);
 760
 761         /* Get the actual shift_clk_div and clock rates. */
 762         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
 763         dsi->target_lp_clk_khz =
 764                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
 765         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
 766
 767         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
 768                                         dsi->target_hs_clk_khz);
 769
 770         /*
 771          * Force video clock to be continuous mode if
 772          * enable_hs_clock_on_lp_cmd_mode is set
 773          */
 774         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 775                 if (dsi->info.video_clock_mode !=
 776                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
 777                         dev_warn(&dc->ndev->dev,
 778                                 "Force clock continuous mode\n");
 779
 780                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
 781         }
 782 }
 783
 784 static void tegra_dsi_init_sw(struct tegra_dc *dc,
 785                         struct tegra_dc_dsi_data *dsi)
 786 {
 787         dsi->ulpm = false;
 788         dsi->enabled = false;
 789         dsi->clk_ref = false;
 790
 791 #if DSI_USE_SYNC_POINTS
 792         dsi->syncpt_id = nvhost_get_syncpt_client_managed("dsi");
 793 #endif
 794
 795         tegra_dsi_init_clock_param(dc);
 796
 797         atomic_set(&dsi->host_ref, 0);
 798         dsi->host_suspended = false;
 799         mutex_init(&dsi->host_lock);
 800         init_completion(&dc->out->user_vblank_comp);
 801         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
 802         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
 803 }
 804
 805 #define SELECT_T_PHY(platform_t_phy_ps, default_phy, clk_ps, hw_inc) ( \
 806 (platform_t_phy_ps) ? ( \
 807 ((DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)) < 0 ? 0 : \
 808 (DSI_CONVERT_T_PHY_PS_TO_T_PHY(platform_t_phy_ps, clk_ps, hw_inc)))) : \
 809 ((default_phy) < 0 ? 0 : (default_phy)))
 810
 811 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
 812                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 813 {
 814         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 815                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 816                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 817
 818         phy_timing_clk->t_clktrail = SELECT_T_PHY(
 819                 dsi->info.phy_timing.t_clktrail_ns * 1000,
 820                 T_CLKTRAIL_DEFAULT(clk_ps), clk_ps, T_CLKTRAIL_HW_INC);
 821
 822         phy_timing_clk->t_clkpost = SELECT_T_PHY(
 823                 dsi->info.phy_timing.t_clkpost_ns * 1000,
 824                 T_CLKPOST_DEFAULT(clk_ps), clk_ps, T_CLKPOST_HW_INC);
 825
 826         phy_timing_clk->t_clkzero = SELECT_T_PHY(
 827                 dsi->info.phy_timing.t_clkzero_ns * 1000,
 828                 T_CLKZERO_DEFAULT(clk_ps), clk_ps, T_CLKZERO_HW_INC);
 829
 830         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
 831                 dsi->info.phy_timing.t_clkprepare_ns * 1000,
 832                 T_CLKPREPARE_DEFAULT(clk_ps), clk_ps, T_CLKPREPARE_HW_INC);
 833
 834         phy_timing_clk->t_clkpre = SELECT_T_PHY(
 835                 dsi->info.phy_timing.t_clkpre_ns * 1000,
 836                 T_CLKPRE_DEFAULT, clk_ps, T_CLKPRE_HW_INC);
 837 }
 838
 839 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
 840                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 841 {
 842         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 843                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 844                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 845
 846         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
 847                 dsi->info.phy_timing.t_hsdexit_ns * 1000,
 848                 T_HSEXIT_DEFAULT(clk_ps), clk_ps, T_HSEXIT_HW_INC);
 849
 850         phy_timing_clk->t_hstrail = SELECT_T_PHY(
 851                 dsi->info.phy_timing.t_hstrail_ns * 1000,
 852                 T_HSTRAIL_DEFAULT(clk_ps), clk_ps, T_HSTRAIL_HW_INC);
 853
 854         phy_timing_clk->t_datzero = SELECT_T_PHY(
 855                 dsi->info.phy_timing.t_datzero_ns * 1000,
 856                 T_DATZERO_DEFAULT(clk_ps), clk_ps, T_DATZERO_HW_INC);
 857
 858         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
 859                 dsi->info.phy_timing.t_hsprepare_ns * 1000,
 860                 T_HSPREPARE_DEFAULT(clk_ps), clk_ps, T_HSPREPARE_HW_INC);
 861 }
 862
 863 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
 864                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 865 {
 866         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 867                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 868                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 869 }
 870
 871 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
 872                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 873 {
 874         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 875                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 876                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 877
 878         phy_timing_clk->t_taget = SELECT_T_PHY(
 879                 dsi->info.phy_timing.t_taget_ns * 1000,
 880                 T_TAGET_DEFAULT(clk_ps), clk_ps, T_TAGET_HW_INC);
 881
 882         phy_timing_clk->t_tasure = SELECT_T_PHY(
 883                 dsi->info.phy_timing.t_tasure_ns * 1000,
 884                 T_TASURE_DEFAULT(clk_ps), clk_ps, T_TASURE_HW_INC);
 885
 886         phy_timing_clk->t_tago = SELECT_T_PHY(
 887                 dsi->info.phy_timing.t_tago_ns * 1000,
 888                 T_TAGO_DEFAULT(clk_ps), clk_ps, T_TAGO_HW_INC);
 889 }
 890
 891 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
 892                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ps)
 893 {
 894         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 895                 dsi->info.phy_timing.t_tlpx_ns * 1000,
 896                 T_TLPX_DEFAULT(clk_ps), clk_ps, T_TLPX_HW_INC);
 897
 898         phy_timing_clk->t_wakeup = SELECT_T_PHY(
 899                 dsi->info.phy_timing.t_wakeup_ns * 1000,
 900                 T_WAKEUP_DEFAULT, clk_ps, T_WAKEUP_HW_INC);
 901 }
 902
 903 #undef SELECT_T_PHY
 904
 905 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
 906                                 struct dsi_phy_timing_inclk *phy_timing_clk,
 907                                 u32 clk_ps, u8 lphs)
 908 {
 909         if (tegra_platform_is_fpga()) {
 910                 clk_ps = (1000 * 1000 * 1000) / (dsi->info.fpga_freq_khz ?
 911                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
 912         }
 913
 914         if (lphs == DSI_LPHS_IN_HS_MODE) {
 915                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ps);
 916                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ps);
 917         } else {
 918                 /* default is LP mode */
 919                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ps);
 920                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ps);
 921                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ps);
 922                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 923                         tegra_dsi_get_clk_phy_timing(dsi,
 924                                         phy_timing_clk, clk_ps);
 925         }
 926 }
 927
 928 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
 929                                 struct dsi_phy_timing_inclk *phy_timing,
 930                                 u32 clk_ps, u8 lphs)
 931 {
 932         int err = 0;
 933
 934 #define CHECK_RANGE(val, min, max) ( \
 935                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
 936                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 937
 938         if (tegra_platform_is_fpga())
 939                 clk_ps = dsi->info.fpga_freq_khz ?
 940                         ((1000 * 1000 * 1000) / dsi->info.fpga_freq_khz) :
 941                         DEFAULT_FPGA_FREQ_KHZ;
 942
 943         err = CHECK_RANGE(
 944         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 945                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC),
 946                         MIPI_T_TLPX_PS_MIN, MIPI_T_TLPX_PS_MAX);
 947         if (err < 0) {
 948                 dev_warn(&dsi->dc->ndev->dev,
 949                         "dsi: Tlpx mipi range violated\n");
 950                 goto fail;
 951         }
 952
 953         if (lphs == DSI_LPHS_IN_HS_MODE) {
 954                 err = CHECK_RANGE(
 955                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 956                         phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC),
 957                         MIPI_T_HSEXIT_PS_MIN, MIPI_T_HSEXIT_PS_MAX);
 958                 if (err < 0) {
 959                         dev_warn(&dsi->dc->ndev->dev,
 960                                 "dsi: HsExit mipi range violated\n");
 961                         goto fail;
 962                 }
 963
 964                 err = CHECK_RANGE(
 965                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 966                         phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC),
 967                         MIPI_T_HSTRAIL_PS_MIN(clk_ps), MIPI_T_HSTRAIL_PS_MAX);
 968                 if (err < 0) {
 969                         dev_warn(&dsi->dc->ndev->dev,
 970                                 "dsi: HsTrail mipi range violated\n");
 971                         goto fail;
 972                 }
 973
 974                 err = CHECK_RANGE(
 975                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 976                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
 977                         MIPI_T_HSZERO_PS_MIN, MIPI_T_HSZERO_PS_MAX);
 978                 if (err < 0) {
 979                         dev_warn(&dsi->dc->ndev->dev,
 980                                 "dsi: HsZero mipi range violated\n");
 981                         goto fail;
 982                 }
 983
 984                 err = CHECK_RANGE(
 985                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 986                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC),
 987                         MIPI_T_HSPREPARE_PS_MIN(clk_ps),
 988                         MIPI_T_HSPREPARE_PS_MAX(clk_ps));
 989                 if (err < 0) {
 990                         dev_warn(&dsi->dc->ndev->dev,
 991                                 "dsi: HsPrepare mipi range violated\n");
 992                         goto fail;
 993                 }
 994
 995                 err = CHECK_RANGE(
 996                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 997                         phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
 998                         DSI_CONVERT_T_PHY_TO_T_PHY_PS(
 999                         phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC),
1000                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MIN(clk_ps),
1001                         MIPI_T_HSPREPARE_ADD_HSZERO_PS_MAX);
1002                 if (err < 0) {
1003                         dev_warn(&dsi->dc->ndev->dev,
1004                         "dsi: HsPrepare + HsZero mipi range violated\n");
1005                         goto fail;
1006                 }
1007         } else {
1008                 /* default is LP mode */
1009                 err = CHECK_RANGE(
1010                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1011                         phy_timing->t_wakeup, clk_ps, T_WAKEUP_HW_INC),
1012                         MIPI_T_WAKEUP_PS_MIN, MIPI_T_WAKEUP_PS_MAX);
1013                 if (err < 0) {
1014                         dev_warn(&dsi->dc->ndev->dev,
1015                                 "dsi: WakeUp mipi range violated\n");
1016                         goto fail;
1017                 }
1018
1019                 err = CHECK_RANGE(
1020                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1021                         phy_timing->t_tasure, clk_ps, T_TASURE_HW_INC),
1022                         MIPI_T_TASURE_PS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1023                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)),
1024                         MIPI_T_TASURE_PS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1025                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC)));
1026                 if (err < 0) {
1027                         dev_warn(&dsi->dc->ndev->dev,
1028                                 "dsi: TaSure mipi range violated\n");
1029                         goto fail;
1030                 }
1031         }
1032
1033         if (lphs == DSI_LPHS_IN_HS_MODE ||
1034                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
1035                 err = CHECK_RANGE(
1036                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1037                         phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC),
1038                         MIPI_T_CLKTRAIL_PS_MIN, MIPI_T_CLKTRAIL_PS_MAX);
1039                 if (err < 0) {
1040                         dev_warn(&dsi->dc->ndev->dev,
1041                                 "dsi: ClkTrail mipi range violated\n");
1042                         goto fail;
1043                 }
1044
1045                 err = CHECK_RANGE(
1046                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1047                         phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC),
1048                         MIPI_T_CLKPOST_PS_MIN(clk_ps), MIPI_T_CLKPOST_PS_MAX);
1049                 if (err < 0) {
1050                         dev_warn(&dsi->dc->ndev->dev,
1051                                 "dsi: ClkPost mipi range violated\n");
1052                         goto fail;
1053                 }
1054
1055                 err = CHECK_RANGE(
1056                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1057                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1058                         MIPI_T_CLKZERO_PS_MIN, MIPI_T_CLKZERO_PS_MAX);
1059                 if (err < 0) {
1060                         dev_warn(&dsi->dc->ndev->dev,
1061                                 "dsi: ClkZero mipi range violated\n");
1062                         goto fail;
1063                 }
1064
1065                 err = CHECK_RANGE(
1066                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1067                         phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC),
1068                         MIPI_T_CLKPREPARE_PS_MIN, MIPI_T_CLKPREPARE_PS_MAX);
1069                 if (err < 0) {
1070                         dev_warn(&dsi->dc->ndev->dev,
1071                                 "dsi: ClkPrepare mipi range violated\n");
1072                         goto fail;
1073                 }
1074
1075                 err = CHECK_RANGE(
1076                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1077                         phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC),
1078                         MIPI_T_CLKPRE_PS_MIN, MIPI_T_CLKPRE_PS_MAX);
1079                 if (err < 0) {
1080                         dev_warn(&dsi->dc->ndev->dev,
1081                                 "dsi: ClkPre mipi range violated\n");
1082                         goto fail;
1083                 }
1084
1085                 err = CHECK_RANGE(
1086                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1087                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1088                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1089                         phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC),
1090                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MIN,
1091                         MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MAX);
1092                 if (err < 0) {
1093                         dev_warn(&dsi->dc->ndev->dev,
1094                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1095                         goto fail;
1096                 }
1097         }
1098 fail:
1099 #undef CHECK_RANGE
1100         return err;
1101 }
1102
1103 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1104                                 struct dsi_phy_timing_inclk *phy_timing,
1105                                 u32 clk_ps, u8 lphs)
1106 {
1107         u32 hs_t_phy_ps = 0;
1108         u32 clk_t_phy_ps = 0;
1109         u32 t_phy_ps;
1110         u32 h_blank_ps;
1111         struct tegra_dc_mode *modes;
1112         u32 t_pix_ps;
1113         int err = 0;
1114
1115         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1116                 goto fail;
1117
1118         if (dsi->info.video_data_type ==
1119                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1120                 dsi->info.video_burst_mode <=
1121                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1122                 goto fail;
1123
1124         modes = dsi->dc->out->modes;
1125         t_pix_ps = clk_ps * BITS_PER_BYTE *
1126                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1127
1128         hs_t_phy_ps =
1129                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1130                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1131                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1132                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1133                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1134                 phy_timing->t_hsprepare, clk_ps, T_HSPREPARE_HW_INC) +
1135                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1136                 phy_timing->t_datzero, clk_ps, T_DATZERO_HW_INC) +
1137                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1138                 phy_timing->t_hstrail, clk_ps, T_HSTRAIL_HW_INC) +
1139                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1140                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC);
1141
1142         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1143                 clk_t_phy_ps =
1144                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1145                 phy_timing->t_clkpost, clk_ps, T_CLKPOST_HW_INC) +
1146                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1147                 phy_timing->t_clktrail, clk_ps, T_CLKTRAIL_HW_INC) +
1148                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1149                 phy_timing->t_hsdexit, clk_ps, T_HSEXIT_HW_INC) +
1150                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1151                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1152                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1153                 phy_timing->t_clkprepare, clk_ps, T_CLKPREPARE_HW_INC) +
1154                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1155                 phy_timing->t_clkzero, clk_ps, T_CLKZERO_HW_INC) +
1156                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1157                 phy_timing->t_clkpre, clk_ps, T_CLKPRE_HW_INC);
1158
1159                 /* clk_pre overlaps LP-11 hs mode start sequence */
1160                 hs_t_phy_ps -= DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1161                         phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC);
1162         }
1163
1164         h_blank_ps = t_pix_ps * (modes->h_sync_width + modes->h_back_porch +
1165                                                 modes->h_front_porch);
1166
1167         /* Extra tlpx and byte cycle required by dsi HW */
1168         t_phy_ps = dsi->info.n_data_lanes * (hs_t_phy_ps + clk_t_phy_ps +
1169                 DSI_CONVERT_T_PHY_TO_T_PHY_PS(
1170                 phy_timing->t_tlpx, clk_ps, T_TLPX_HW_INC) +
1171                 clk_ps * BITS_PER_BYTE);
1172
1173         if (h_blank_ps < t_phy_ps) {
1174                 err = -EINVAL;
1175                 dev_WARN(&dsi->dc->ndev->dev,
1176                         "dsi: Hblank is smaller than HS phy timing: %u pix\n",
1177                                         (t_phy_ps - h_blank_ps) / t_pix_ps);
1178                 goto fail;
1179         }
1180
1181         return 0;
1182 fail:
1183         return err;
1184 }
1185
1186 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1187                                 struct dsi_phy_timing_inclk *phy_timing,
1188                                 u32 clk_ps, u8 lphs)
1189 {
1190         int err = 0;
1191
1192         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ps, lphs);
1193         if (err < 0) {
1194                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1195                 goto fail;
1196         }
1197
1198         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ps, lphs);
1199         if (err < 0) {
1200                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1201                 goto fail;
1202         }
1203
1204         /* TODO: add more contraints */
1205 fail:
1206         return err;
1207 }
1208
1209 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1210 {
1211         u32 val;
1212         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1213
1214         tegra_dsi_get_phy_timing
1215                 (dsi, &phy_timing, dsi->current_bit_clk_ps, lphs);
1216
1217         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1218                                         dsi->current_bit_clk_ps, lphs);
1219
1220         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1221                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1222                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1223                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1224                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1225
1226                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1227                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1228                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1229                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1230
1231                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1232                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1233                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1234
1235                 phy_timing.t_taget += T_TAGET_HW_INC;
1236                 phy_timing.t_tasure += T_TASURE_HW_INC;
1237                 phy_timing.t_tago += T_TAGO_HW_INC;
1238         }
1239         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1240                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1241                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1242                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1243         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1244
1245         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1246                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1247                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1248                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1249         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1250
1251         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1252                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1253                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1254         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1255
1256         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1257                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1258                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1259         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1260
1261         dsi->phy_timing = phy_timing;
1262 }
1263
1264 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1265                                 struct tegra_dc_dsi_data *dsi)
1266 {
1267         u32 dsi_to_pixel_clk_ratio;
1268         u32 temp;
1269         u32 temp1;
1270         u32 mipi_clk_adj_kHz = 0;
1271         u32 sol_delay;
1272         struct tegra_dc_mode *dc_modes = &dc->mode;
1273
1274         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1275         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1276                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1277
1278         /* Convert Fdsi to byte format */
1279         dsi_to_pixel_clk_ratio *= 1000/8;
1280
1281         /* Multiplying by 1000 so that we don't loose the fraction part */
1282         temp = dc_modes->h_active * 1000;
1283         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1284                         dc_modes->h_sync_width;
1285
1286         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1287                         temp * dsi->pixel_scaler_mul /
1288                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1289
1290         /* Do rounding on sol delay */
1291         sol_delay = (sol_delay + 1000 - 1)/1000;
1292
1293         /* TODO:
1294          * 1. find out the correct sol fifo depth to use
1295          * 2. verify with hw about the clamping function
1296          */
1297         if (sol_delay > (480 * 4)) {
1298                 sol_delay = (480 * 4);
1299                 mipi_clk_adj_kHz = sol_delay +
1300                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1301                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1302
1303                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1304
1305                 mipi_clk_adj_kHz *= 4;
1306         }
1307
1308         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1309
1310         return sol_delay;
1311 }
1312
1313 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1314                                 struct tegra_dc_dsi_data *dsi)
1315 {
1316         u32 sol_delay;
1317         u32 internal_delay;
1318         u32 h_width_byte_clk;
1319         u32 h_width_pixels;
1320         u32 h_width_ganged_byte_clk;
1321         u8 n_data_lanes_this_cont = 0;
1322         u8 n_data_lanes_ganged = 0;
1323
1324         if (!(dsi->info.ganged_type)) {
1325                 if (dsi->info.video_burst_mode ==
1326                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1327                         dsi->info.video_burst_mode ==
1328                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1329 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1330                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1331                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1332 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1333                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1334                 } else {
1335                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1336                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1337                 }
1338         } else {
1339 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1340 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1341 #define FIFO_WR_PIX_CLK_DELAY 2
1342 #define FIFO_RD_BYTE_CLK_DELAY 6
1343 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1344                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1345                                 FIFO_WR_PIX_CLK_DELAY)
1346
1347                 internal_delay = DIV_ROUND_UP(
1348                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1349                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1350                                 + FIFO_RD_BYTE_CLK_DELAY;
1351
1352                 h_width_pixels = dc->mode.h_sync_width +
1353                                         dc->mode.h_back_porch +
1354                                         dc->mode.h_active +
1355                                         dc->mode.h_front_porch;
1356
1357                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1358                                         dsi->pixel_scaler_mul,
1359                                         dsi->pixel_scaler_div *
1360                                         dsi->info.n_data_lanes);
1361
1362                 if (dsi->info.ganged_type ==
1363                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1364                         dsi->info.ganged_type ==
1365                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD ||
1366                         dsi->info.ganged_type ==
1367                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
1368                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1369                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1370                 }
1371
1372                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1373                                         n_data_lanes_this_cont *
1374                                         h_width_byte_clk,
1375                                         n_data_lanes_ganged);
1376
1377                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1378                                                         internal_delay;
1379                 sol_delay = (dsi->info.video_data_type ==
1380                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1381                                 sol_delay + 20 : sol_delay;
1382
1383 #undef SOL_TO_VALID_PIX_CLK_DELAY
1384 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1385 #undef FIFO_WR_PIX_CLK_DELAY
1386 #undef FIFO_RD_BYTE_CLK_DELAY
1387 #undef TOT_INTERNAL_PIX_DELAY
1388         }
1389
1390         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1391                                                 DSI_SOL_DELAY);
1392 }
1393
1394 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1395 {
1396         u32 val;
1397         u32 bytes_per_frame;
1398         u32 timeout = 0;
1399
1400         /* TODO: verify the following equation */
1401         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1402                                                 (dsi->info.refresh_rate * 8);
1403         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1404         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1405
1406         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1407                         DSI_TIMEOUT_0_HTX_TO(timeout);
1408         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1409
1410         if (dsi->info.panel_reset_timeout_msec)
1411                 timeout = (dsi->info.panel_reset_timeout_msec * 1000 * 1000 *
1412                                          1000) / dsi->current_bit_clk_ps;
1413         else
1414                 timeout = DSI_PR_TO_VALUE;
1415
1416         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1417                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1418         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1419
1420         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1421                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1422                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1423                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1424         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1425 }
1426
1427 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1428                                                 struct tegra_dc_dsi_data *dsi)
1429 {
1430         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1431         u32 hact_pkt_len_pix = 0;
1432         u32 hact_pkt_len_bytes = 0;
1433         u32 hfp_pkt_len_bytes = 0;
1434         u32 pix_per_line_orig = 0;
1435         u32 pix_per_line = 0;
1436         u32 val = 0;
1437         int i = 0;
1438
1439 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1440 #define HEADER_OVERHEAD 16
1441
1442         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1443                         dc->mode.h_active + dc->mode.h_front_porch;
1444
1445         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1446                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1447         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1448
1449         switch (dsi->info.ganged_type) {
1450         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT: /* fall through */
1451         case TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD: /* fall through */
1452                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1453                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1454                 break;
1455         case TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP:
1456                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2) +
1457                         dsi->info.ganged_overlap;
1458                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1459                 break;
1460         default:
1461                 dev_err(&dc->ndev->dev, "dsi: invalid ganged type\n");
1462         }
1463
1464         for (i = 0; i < dsi->max_instances; i++) {
1465                 hact_pkt_len_bytes = hact_pkt_len_pix *
1466                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1467                 hfp_pkt_len_bytes = pix_per_line *
1468                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1469                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1470
1471                 val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1472                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1473                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_2_3, i);
1474
1475                 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1476                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1477                 tegra_dsi_controller_writel(dsi, val, DSI_PKT_LEN_4_5, i);
1478
1479                 if (dsi->info.ganged_type !=
1480                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
1481                         hact_pkt_len_pix =
1482                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1483                         pix_per_line = pix_per_line_orig - pix_per_line;
1484                 }
1485         }
1486
1487         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1488                 DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1489         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1490
1491 #undef HEADER_OVERHEAD
1492 }
1493
1494 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1495                                                 struct tegra_dc_dsi_data *dsi)
1496 {
1497         u32 val;
1498         u32 hact_pkt_len;
1499         u32 hsa_pkt_len;
1500         u32 hbp_pkt_len;
1501         u32 hfp_pkt_len;
1502
1503         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1504                                                         dsi->pixel_scaler_div;
1505         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1506                                                         dsi->pixel_scaler_div;
1507         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1508                                                         dsi->pixel_scaler_div;
1509         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1510                                                         dsi->pixel_scaler_div;
1511
1512         if (dsi->info.video_burst_mode !=
1513                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1514                 hbp_pkt_len += hsa_pkt_len;
1515
1516         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1517         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1518         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1519
1520         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1521                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1522         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1523
1524         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1525                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1526         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1527
1528         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1529                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1530         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1531
1532         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1533         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1534 }
1535
1536 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1537                                                 struct tegra_dc_dsi_data *dsi)
1538 {
1539         unsigned long   val;
1540         unsigned long   act_bytes;
1541
1542         if (dsi->info.ganged_type) {
1543                 act_bytes = DIV_ROUND_UP(dc->mode.h_active, 2);
1544                 act_bytes = (act_bytes) * dsi->pixel_scaler_mul /
1545                                 dsi->pixel_scaler_div + 1;
1546         } else {
1547                 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1548                                 dsi->pixel_scaler_div + 1;
1549         }
1550         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1551         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1552
1553         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1554         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1555
1556         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1557         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1558
1559         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1560         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1561 }
1562
1563 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1564                                 struct tegra_dc_dsi_data *dsi)
1565 {
1566         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1567                 return;
1568
1569         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1570                 if (dsi->info.ganged_type)
1571                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1572                 else
1573                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1574         } else {
1575                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1576         }
1577 }
1578
1579 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1580                                 struct tegra_dc_dsi_data *dsi)
1581 {
1582         const u32 *pkt_seq;
1583         u32 rgb_info;
1584         u32 pkt_seq_3_5_rgb_lo;
1585         u32 pkt_seq_3_5_rgb_hi;
1586         u32     val;
1587         u32 reg;
1588         u8  i;
1589
1590         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1591                 return;
1592
1593         switch (dsi->info.pixel_format) {
1594         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1595                 rgb_info = CMD_RGB_16BPP;
1596                 break;
1597         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1598                 rgb_info = CMD_RGB_18BPP;
1599                 break;
1600         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1601                 rgb_info = CMD_RGB_18BPPNP;
1602                 break;
1603         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1604         default:
1605                 rgb_info = CMD_RGB_24BPP;
1606                 break;
1607         }
1608
1609         pkt_seq_3_5_rgb_lo = 0;
1610         pkt_seq_3_5_rgb_hi = 0;
1611         if (dsi->info.pkt_seq)
1612                 pkt_seq = dsi->info.pkt_seq;
1613         else if (dsi->info.video_data_type ==
1614                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1615                         pkt_seq = dsi_pkt_seq_cmd_mode;
1616         } else {
1617                 switch (dsi->info.video_burst_mode) {
1618                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1619                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1620                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1621                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1622                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1623                         pkt_seq_3_5_rgb_lo =
1624                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1625                         if (!dsi->info.no_pkt_seq_eot)
1626                                 pkt_seq = dsi_pkt_seq_video_burst;
1627                         else
1628                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1629                         break;
1630                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1631                         pkt_seq_3_5_rgb_hi =
1632                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1633                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1634                         break;
1635                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1636                 default:
1637                         if (dsi->info.ganged_type) {
1638                                 pkt_seq_3_5_rgb_lo =
1639                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1640                                 pkt_seq =
1641                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1642                         } else {
1643                                 pkt_seq_3_5_rgb_lo =
1644                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1645                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1646                         }
1647
1648                         /* Simulator does not support EOT packet yet */
1649                         if (tegra_cpu_is_asim())
1650                                 pkt_seq = dsi_pkt_seq_video_non_burst_no_eot;
1651                         break;
1652                 }
1653         }
1654
1655         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1656                 val = pkt_seq[i];
1657                 reg = dsi_pkt_seq_reg[i];
1658                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1659                         val |= pkt_seq_3_5_rgb_lo;
1660                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1661                         val |= pkt_seq_3_5_rgb_hi;
1662                 tegra_dsi_writel(dsi, val, reg);
1663         }
1664 }
1665
1666 static void tegra_dsi_reset_underflow_overflow
1667                                 (struct tegra_dc_dsi_data *dsi)
1668 {
1669         u32 val;
1670
1671         val = tegra_dsi_readl(dsi, DSI_STATUS);
1672         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1673         if (val) {
1674                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1675                         dev_warn(&dsi->dc->ndev->dev,
1676                                 "dsi: video fifo overflow. Resetting flag\n");
1677                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1678                         dev_warn(&dsi->dc->ndev->dev,
1679                                 "dsi: video fifo underflow. Resetting flag\n");
1680                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1681                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1682                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1683                 udelay(5);
1684         }
1685 }
1686
1687 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1688 {
1689         u32 trigger;
1690         u32 val;
1691         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1692         struct tegra_dc_mode mode = dsi->dc->mode;
1693         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1694                                 mode.v_active + mode.v_front_porch;
1695         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1696         u32 timeout_cnt = 0;
1697
1698 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1699 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1700
1701         val = tegra_dsi_readl(dsi, DSI_STATUS);
1702         while (!(val & DSI_STATUS_IDLE(0x1))) {
1703                 cpu_relax();
1704                 udelay(line_period);
1705                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1706                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1707                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1708                         break;
1709                 }
1710         }
1711
1712         tegra_dsi_writel(dsi,
1713                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1714                 DSI_POWER_CONTROL);
1715         /* stabilization delay */
1716         udelay(300);
1717
1718         tegra_dsi_writel(dsi,
1719                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1720                 DSI_POWER_CONTROL);
1721         /* stabilization delay */
1722         udelay(300);
1723
1724         /* dsi HW does not clear host trigger bit automatically
1725          * on dsi interface disable if host fifo is empty or in mid
1726          * of host transmission
1727          */
1728         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1729         if (trigger)
1730                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1731
1732 #undef DSI_IDLE_TIMEOUT
1733 }
1734
1735 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1736                                         struct tegra_dc_dsi_data *dsi)
1737 {
1738         tegra_dc_get(dc);
1739
1740         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1741         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1742         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1743
1744         /* stabilization delay */
1745         udelay(500);
1746
1747         tegra_dc_put(dc);
1748
1749         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1750 }
1751
1752 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1753  * whichever happens to occur first
1754  */
1755 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1756                                 struct tegra_dc_dsi_data *dsi,
1757                                 u32 timeout_n_frames)
1758 {
1759         long timeout;
1760         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1761         struct tegra_dc_mode mode = dc->mode;
1762         u32 line_period = DIV_ROUND_UP(
1763                                 MS_TO_US(frame_period),
1764                                 mode.v_sync_width + mode.v_back_porch +
1765                                 mode.v_active + mode.v_front_porch);
1766
1767         if (timeout_n_frames < 2)
1768                 dev_WARN(&dc->ndev->dev,
1769                 "dsi: to stop at next frame give at least 2 frame delay\n");
1770
1771         timeout = _tegra_dc_wait_for_frame_end(dc, timeout_n_frames *
1772                 frame_period);
1773
1774         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1775         udelay(mode.v_ref_to_sync * line_period);
1776
1777         return timeout;
1778 }
1779
1780 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1781                                                 struct tegra_dc_dsi_data *dsi,
1782                                                 u32 timeout_n_frames)
1783 {
1784         tegra_dsi_stop_dc_stream(dc, dsi);
1785
1786         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1787
1788         tegra_dsi_soft_reset(dsi);
1789
1790         tegra_dsi_reset_underflow_overflow(dsi);
1791 }
1792
1793 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1794 {
1795         int err;
1796
1797         /* convert to spio */
1798         err = gpio_request(gpio, "temp_request");
1799         if (err < 0) {
1800                 dev_err(&dsi->dc->ndev->dev,
1801                         "dsi: %s: gpio request failed %d\n", __func__, err);
1802                 return;
1803         }
1804         gpio_free(gpio);
1805 }
1806
1807 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1808                                         struct tegra_dc_dsi_data *dsi)
1809 {
1810         u32 val;
1811
1812         tegra_dc_get(dc);
1813         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
1814
1815         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1816
1817         /* TODO: clean up */
1818         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1819                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1820                         DC_CMD_DISPLAY_POWER_CONTROL);
1821
1822         /* Configure one-shot mode or continuous mode */
1823         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1824                 /* disable LSPI/LCD_DE output */
1825                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1826                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1827
1828                 /* enable MSF & set MSF polarity */
1829                 val = MSF_ENABLE | MSF_LSPI;
1830                 if (!dsi->info.te_polarity_low)
1831                         val |= MSF_POLARITY_HIGH;
1832                 else
1833                         val |= MSF_POLARITY_LOW;
1834                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1835
1836                 /* set non-continuous mode */
1837                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1838                                                 DC_CMD_DISPLAY_COMMAND);
1839
1840                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1841
1842                 if (dsi->info.te_gpio)
1843                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1844         } else {
1845                 /* set continuous mode */
1846                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1847                                                 DC_CMD_DISPLAY_COMMAND);
1848                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1849         }
1850
1851         tegra_dc_put(dc);
1852
1853         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1854 }
1855
1856 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1857                                 struct tegra_dc_dsi_data *dsi)
1858 {
1859         u32 shift_clk_div_register;
1860         u32 val;
1861
1862         /* formula: (dsi->shift_clk_div - 1) * 2 */
1863         shift_clk_div_register = DIV_ROUND_CLOSEST(
1864                                 ((dsi->shift_clk_div.mul -
1865                                 dsi->shift_clk_div.div) * 2),
1866                                 dsi->shift_clk_div.div);
1867
1868         if (tegra_platform_is_fpga()) {
1869                 shift_clk_div_register = 1;
1870                 if (dsi->info.ganged_type)
1871                         shift_clk_div_register = 0;
1872         }
1873
1874         tegra_dc_get(dc);
1875
1876         val = PIXEL_CLK_DIVIDER_PCD1 |
1877                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1878
1879         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1880          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1881          * After 2us delay, write the target values to it. */
1882 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_11x_SOC)
1883         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1884         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1885
1886         udelay(2);
1887 #endif
1888
1889         /* TODO: find out if PCD3 option is required */
1890         val = PIXEL_CLK_DIVIDER_PCD1 |
1891                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1892
1893         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1894
1895         tegra_dc_put(dc);
1896 }
1897
1898 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1899                         struct tegra_dc_dsi_data *dsi, u32 clk)
1900 {
1901         u32 rm;
1902         u32 pclk_khz;
1903
1904         /* Round up to MHz */
1905         rm = clk % 1000;
1906         if (rm != 0)
1907                 clk -= rm;
1908
1909         /* Set up pixel clock */
1910         pclk_khz = (clk * dsi->shift_clk_div.div) /
1911                                 dsi->shift_clk_div.mul;
1912
1913         dc->mode.pclk = pclk_khz * 1000;
1914
1915         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1916         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1917
1918         /* TODO: Define one shot work delay in board file. */
1919         /* Since for one-shot mode, refresh rate is usually set larger than
1920          * expected refresh rate, it needs at least 3 frame period. Less
1921          * delay one shot work is, more powering saving we have. */
1922         dc->one_shot_delay_ms = 4 *
1923                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1924
1925         tegra_dsi_setup_clk(dc, dsi);
1926         tegra_dsi_reset_deassert(dsi);
1927
1928         dsi->current_dsi_clk_khz =
1929                         clk_get_rate(dsi->dsi_clk[0]) / 1000;
1930         dsi->current_bit_clk_ps =  DIV_ROUND_CLOSEST((1000 * 1000 * 1000),
1931                                         (dsi->current_dsi_clk_khz * 2));
1932 }
1933
1934 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1935 {
1936         u32 val;
1937
1938         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1939         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1940
1941         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1942                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1943                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1944         } else {
1945                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1946                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1947         }
1948         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1949
1950         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1951         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1952         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1953         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1954
1955         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1956 }
1957
1958 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1959 {
1960         u32 val;
1961         tegra_dsi_hs_clk_out_enable(dsi);
1962
1963         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1964         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1965         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1966         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1967 }
1968
1969 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1970                                                 struct tegra_dc_dsi_data *dsi)
1971 {
1972         u32 val;
1973
1974         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1975                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1976
1977         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1978         /* stabilization delay */
1979         udelay(300);
1980
1981         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1982         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1983         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1984         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1985
1986         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1987         /* stabilization delay */
1988         udelay(300);
1989
1990         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1991         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1992 }
1993
1994 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1995 {
1996         u32 dsi_control;
1997         u32 host_dsi_control;
1998         u32 max_threshold;
1999
2000         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
2001         host_dsi_control = HOST_DSI_CTRL_COMMON |
2002                         HOST_DSI_CTRL_HOST_DRIVEN |
2003                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
2004         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
2005
2006         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
2007         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2008         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2009
2010         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
2011         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2012         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2013 }
2014
2015 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
2016                                                 u8 driven_mode)
2017 {
2018         u32 dsi_control;
2019         u32 host_dsi_control;
2020         u32 max_threshold;
2021         u32 dcs_cmd;
2022
2023         dsi_control = dsi->dsi_control_val;
2024         host_dsi_control = HOST_DSI_CTRL_COMMON;
2025         max_threshold = 0;
2026         dcs_cmd = 0;
2027
2028         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
2029                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
2030                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
2031                 max_threshold =
2032                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
2033                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
2034         } else {
2035                 dsi_control |= DSI_CTRL_DC_DRIVEN;
2036                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
2037                 max_threshold =
2038                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
2039                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
2040
2041                 if (dsi->info.video_data_type ==
2042                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
2043                         dsi_control |= DSI_CTRL_CMD_MODE;
2044                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
2045                                 DSI_WRITE_MEMORY_START)|
2046                                 DSI_DCS_CMDS_LT3_DCS_CMD(
2047                                 DSI_WRITE_MEMORY_CONTINUE);
2048                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
2049                 } else {
2050                         dsi_control |= DSI_CTRL_VIDEO_MODE;
2051                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
2052                 }
2053         }
2054
2055         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
2056         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
2057         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
2058         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
2059 }
2060
2061 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
2062 {
2063         u32 val;
2064
2065         if (dsi->info.controller_vs == DSI_VS_1) {
2066                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2067                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2068                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2069                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2070                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2071                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2072                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
2073                                                 (TEGRA_DSI_PAD_DISABLE) |
2074                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2075                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
2076                                                 (TEGRA_DSI_PAD_DISABLE);
2077                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2078         } else {
2079                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2080                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2081                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2082                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2083                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2084                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
2085                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
2086                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2087         }
2088 }
2089
2090 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
2091 {
2092         u32 val;
2093
2094         if (dsi->info.controller_vs == DSI_VS_1) {
2095                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2096                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2097                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2098                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2099                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2100                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2101                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2102                                                 TEGRA_DSI_PAD_ENABLE) |
2103                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2104                                                 TEGRA_DSI_PAD_ENABLE) |
2105                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2106                                                 TEGRA_DSI_PAD_ENABLE);
2107                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2108         } else {
2109                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2110                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2111                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2112                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2113                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2114                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2115                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2116                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2117         }
2118 }
2119
2120 static void __maybe_unused
2121 tegra_dsi_mipi_calibration_status(struct tegra_dc_dsi_data *dsi)
2122 {
2123         u32 val = 0;
2124         u32 timeout = 0;
2125         /* Start calibration */
2126         val = tegra_mipi_cal_read(dsi->mipi_cal,
2127                 MIPI_CAL_MIPI_CAL_CTRL_0);
2128         val |= (MIPI_CAL_STARTCAL(0x1));
2129         tegra_mipi_cal_write(dsi->mipi_cal, val,
2130                 MIPI_CAL_MIPI_CAL_CTRL_0);
2131
2132         for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2133                         timeout; timeout -= 100) {
2134                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2135                 MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2136                 if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2137                         (val & MIPI_AUTO_CAL_DONE(0x1))) {
2138                                 dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2139                                 break;
2140                 }
2141                 usleep_range(10, 100);
2142         }
2143         if (timeout <= 0)
2144                 dev_info(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2145 }
2146
2147 #if defined(CONFIG_ARCH_TEGRA_13x_SOC)
2148 void tegra_dsi_mipi_calibration_13x(struct tegra_dc_dsi_data *dsi)
2149 {
2150         u32 val, reg;
2151         struct clk *clk72mhz = NULL;
2152
2153         clk72mhz = clk_get_sys("clk72mhz", NULL);
2154         if (IS_ERR_OR_NULL(clk72mhz)) {
2155                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2156                 return;
2157         }
2158         clk_prepare_enable(clk72mhz);
2159
2160         /* Calibration settings begin */
2161         val = tegra_mipi_cal_read(dsi->mipi_cal,
2162                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2163         val &= ~(PAD_DRIV_UP_REF(0x7) | PAD_DRIV_DN_REF(0x7));
2164         val |= (PAD_DRIV_UP_REF(0x3) | PAD_DRIV_DN_REF(0x0));
2165         tegra_mipi_cal_write(dsi->mipi_cal, val,
2166                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2167
2168         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2169                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2170                 DSI_PAD_OUTADJCLK(0x0));
2171         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2172
2173         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2174         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2175                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2176         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2177
2178         /* Deselect shared clk lane with DSI pads */
2179         for (reg = MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0;
2180                 reg <= MIPI_CAL_CSIE_MIPI_CAL_CONFIG_2_0;
2181                 reg += 4) {
2182                 val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2183                 val &= ~(MIPI_CAL_SELA(0x1));
2184                 tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2185         }
2186
2187         /* Calibrate DSI 0 */
2188         if (dsi->info.ganged_type ||
2189                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2190                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2191                         MIPI_CAL_SELDSIA(0x1) |
2192                         MIPI_CAL_HSPDOSDSIA(0x0) |
2193                         MIPI_CAL_HSPUOSDSIA(0x0) |
2194                         MIPI_CAL_TERMOSDSIA(0x0);
2195                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2196                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2197                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2198                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2199
2200                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2201                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2202                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2203                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2204                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2205                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2206                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2207
2208                 /* Deselect PAD C */
2209                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2210                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2211                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2212                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2213                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2214
2215                 /* Deselect PAD D */
2216                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2217                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2218                 val &= ~(MIPI_CAL_SELDSID(0x1));
2219                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2220                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2221
2222                 val = MIPI_CAL_NOISE_FLT(0xa) |
2223                           MIPI_CAL_PRESCALE(0x2) |
2224                           MIPI_CAL_CLKEN_OVR(0x1) |
2225                           MIPI_CAL_AUTOCAL_EN(0x0);
2226                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2227                         MIPI_CAL_MIPI_CAL_CTRL_0);
2228
2229                 tegra_dsi_mipi_calibration_status(dsi);
2230         }
2231         /* Calibrate DSI 1 */
2232         if (dsi->info.ganged_type ||
2233                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2234                 val = MIPI_CAL_OVERIDEC(0x0) |
2235                         MIPI_CAL_SELC(0x1) |
2236                         MIPI_CAL_HSPDOSC(0x0) |
2237                         MIPI_CAL_HSPUOSC(0x0) |
2238                         MIPI_CAL_TERMOSC(0x0);
2239                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2240                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2241                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2242                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2243
2244                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2245                                 MIPI_CAL_HSCLKPDOSDSIA(0x3) |
2246                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2247                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2248                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2249                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2250                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2251
2252                 /* Deselect PAD A */
2253                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2254                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2255                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2256                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2257                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2258
2259                 /* Deselect PAD B */
2260                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2261                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2262                 val &= ~(MIPI_CAL_SELDSID(0x1));
2263                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2264                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2265
2266                 val = MIPI_CAL_NOISE_FLT(0xa) |
2267                           MIPI_CAL_PRESCALE(0x2) |
2268                           MIPI_CAL_CLKEN_OVR(0x1) |
2269                           MIPI_CAL_AUTOCAL_EN(0x0);
2270                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2271                         MIPI_CAL_MIPI_CAL_CTRL_0);
2272
2273                 tegra_dsi_mipi_calibration_status(dsi);
2274         }
2275
2276         clk_disable_unprepare(clk72mhz);
2277 }
2278 #endif
2279
2280 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
2281 static void tegra_dsi_mipi_calibration_21x(struct tegra_dc_dsi_data *dsi)
2282 {
2283         u32 val = 0;
2284         struct clk *clk72mhz = NULL;
2285         char *of_panel_name;
2286         clk72mhz = clk_get_sys("clk72mhz", NULL);
2287         if (IS_ERR_OR_NULL(clk72mhz)) {
2288                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2289                 return;
2290         }
2291         clk_prepare_enable(clk72mhz);
2292
2293         /* Calibration settings begin */
2294         val = tegra_mipi_cal_read(dsi->mipi_cal,
2295                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2296         val &= ~(PAD_VCLAMP_LEVEL(0x7) | PAD_VAUXP_LEVEL(0x7));
2297         val |= (PAD_VCLAMP_LEVEL(0x1) | PAD_VAUXP_LEVEL(0x1));
2298         tegra_mipi_cal_write(dsi->mipi_cal, val,
2299                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2300
2301         val = tegra_mipi_cal_read(dsi->mipi_cal,
2302                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2303         val &= ~(PAD_DRIV_UP_REF(0x7) | PAD_DRIV_DN_REF(0x7));
2304         val |= (PAD_DRIV_UP_REF(0x3) | PAD_DRIV_DN_REF(0x0));
2305         tegra_mipi_cal_write(dsi->mipi_cal, val,
2306                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2307
2308         val = 0;
2309         of_panel_name = of_get_panel_name();
2310         if (of_panel_name)
2311                 if (!strcmp(of_panel_name, AUO_12X19_DSI_PANEL))
2312                         val = (DSI_PAD_OUTADJ3(0x4) | DSI_PAD_OUTADJ2(0x4) |
2313                                 DSI_PAD_OUTADJ1(0x4) | DSI_PAD_OUTADJ0(0x4));
2314         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_1_VS1);
2315         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2_VS1);
2316
2317         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2318         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2319                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2320         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2321
2322         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4_VS1);
2323
2324         /* Calibrate DSI 0 */
2325         if (dsi->info.ganged_type ||
2326                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2327                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2328                         MIPI_CAL_SELDSIA(0x1) |
2329                         MIPI_CAL_HSPDOSDSIA(0x0) |
2330                         MIPI_CAL_HSPUOSDSIA(0x2) |
2331                         MIPI_CAL_TERMOSDSIA(0x0);
2332                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2333                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2334                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2335                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2336
2337                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2338                                 MIPI_CAL_HSCLKPDOSDSIA(0x0) |
2339                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2340                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2341                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2342                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2343                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2344
2345                 val = MIPI_CAL_NOISE_FLT(0xa) |
2346                           MIPI_CAL_PRESCALE(0x2) |
2347                           MIPI_CAL_CLKEN_OVR(0x0) |
2348                           MIPI_CAL_AUTOCAL_EN(0x0);
2349                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2350                         MIPI_CAL_MIPI_CAL_CTRL_0);
2351
2352                 tegra_dsi_mipi_calibration_status(dsi);
2353         }
2354         /* Calibrate DSI 1 */
2355         if (dsi->info.ganged_type ||
2356                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2357                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2358                         MIPI_CAL_SELDSIC(0x1) |
2359                         MIPI_CAL_HSPDOSDSIC(0x0) |
2360                         MIPI_CAL_HSPUOSDSIC(0x2) |
2361                         MIPI_CAL_TERMOSDSIC(0x0);
2362                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2363                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2364                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2365                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2366
2367                 val = (MIPI_CAL_CLKSELDSIC(0x1) |
2368                                 MIPI_CAL_HSCLKPDOSDSIC(0x0) |
2369                                 MIPI_CAL_HSCLKPUOSDSIC(0x2));
2370                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2371                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2_0);
2372                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2373                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_2_0);
2374
2375                 val = MIPI_CAL_NOISE_FLT(0xa) |
2376                           MIPI_CAL_PRESCALE(0x2) |
2377                           MIPI_CAL_CLKEN_OVR(0x0) |
2378                           MIPI_CAL_AUTOCAL_EN(0x0);
2379                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2380                         MIPI_CAL_MIPI_CAL_CTRL_0);
2381
2382                 tegra_dsi_mipi_calibration_status(dsi);
2383         }
2384
2385         clk_disable_unprepare(clk72mhz);
2386 }
2387 #endif
2388
2389 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
2390 static void __maybe_unused
2391 tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
2392 {
2393         u32 val, reg;
2394         struct clk *clk72mhz = NULL;
2395
2396         clk72mhz = clk_get_sys("clk72mhz", NULL);
2397         if (IS_ERR_OR_NULL(clk72mhz)) {
2398                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2399                 return;
2400         }
2401         clk_prepare_enable(clk72mhz);
2402
2403         /* Calibration settings begin */
2404         val = tegra_mipi_cal_read(dsi->mipi_cal,
2405                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2406         val &= ~PAD_DRIV_UP_REF(0x7);
2407         val |= PAD_DRIV_UP_REF(0x3);
2408         tegra_mipi_cal_write(dsi->mipi_cal, val,
2409                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2410         /*Bug 1445912: override tap delay for panel-a-1200-1920-7-0 */
2411         if (dsi->info.boardinfo.platform_boardid == BOARD_P1761 &&
2412                 dsi->info.boardinfo.display_boardversion == 1) {
2413                 val = (DSI_PAD_OUTADJ3(0x4) | DSI_PAD_OUTADJ2(0x4) |
2414                    DSI_PAD_OUTADJ1(0x4) | DSI_PAD_OUTADJ0(0x4));
2415                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_1_VS1);
2416         }
2417
2418         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2419                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2420                 DSI_PAD_OUTADJCLK(0x0));
2421         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2422
2423         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
2424         val |= (DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
2425                    DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2426         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2427
2428         /* Deselect shared clk lane with DSI pads */
2429         for (reg = MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0;
2430                 reg <= MIPI_CAL_CSIE_MIPI_CAL_CONFIG_2_0;
2431                 reg += 4) {
2432                 val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2433                 val &= ~(MIPI_CAL_SELA(0x1));
2434                 tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2435         }
2436
2437         /* Calibrate DSI 0 */
2438         if (dsi->info.ganged_type ||
2439                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2440                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2441                         MIPI_CAL_SELDSIA(0x1) |
2442                         MIPI_CAL_HSPDOSDSIA(0x0) |
2443                         MIPI_CAL_HSPUOSDSIA(0x0) |
2444                         MIPI_CAL_TERMOSDSIA(0x0);
2445                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2446                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2447                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2448                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2449
2450                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2451                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2452                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2453                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2454                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2455                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2456                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2457
2458                 /* Deselect PAD C */
2459                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2460                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2461                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2462                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2463                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2464
2465                 /* Deselect PAD D */
2466                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2467                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2468                 val &= ~(MIPI_CAL_SELDSID(0x1));
2469                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2470                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2471
2472                 val = MIPI_CAL_NOISE_FLT(0xa) |
2473                           MIPI_CAL_PRESCALE(0x2) |
2474                           MIPI_CAL_CLKEN_OVR(0x1) |
2475                           MIPI_CAL_AUTOCAL_EN(0x0);
2476                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2477                         MIPI_CAL_MIPI_CAL_CTRL_0);
2478
2479                 tegra_dsi_mipi_calibration_status(dsi);
2480         }
2481         /* Calibrate DSI 1 */
2482         if (dsi->info.ganged_type ||
2483                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2484                 val = MIPI_CAL_OVERIDEC(0x0) |
2485                         MIPI_CAL_SELC(0x1) |
2486                         MIPI_CAL_HSPDOSC(0x0) |
2487                         MIPI_CAL_HSPUOSC(0x0) |
2488                         MIPI_CAL_TERMOSC(0x0);
2489                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2490                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_0);
2491                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2492                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_0);
2493
2494                 val = (MIPI_CAL_CLKSELDSIA(0x1) |
2495                                 MIPI_CAL_HSCLKPDOSDSIA(0x1) |
2496                                 MIPI_CAL_HSCLKPUOSDSIA(0x2));
2497                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2498                         MIPI_CAL_CILC_MIPI_CAL_CONFIG_2_0);
2499                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2500                         MIPI_CAL_CILD_MIPI_CAL_CONFIG_2_0);
2501
2502                 /* Deselect PAD A */
2503                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2504                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2505                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2506                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2507                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2508
2509                 /* Deselect PAD B */
2510                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2511                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2512                 val &= ~(MIPI_CAL_SELDSID(0x1));
2513                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2514                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2515
2516                 val = MIPI_CAL_NOISE_FLT(0xa) |
2517                           MIPI_CAL_PRESCALE(0x2) |
2518                           MIPI_CAL_CLKEN_OVR(0x1) |
2519                           MIPI_CAL_AUTOCAL_EN(0x0);
2520                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2521                         MIPI_CAL_MIPI_CAL_CTRL_0);
2522
2523                 tegra_dsi_mipi_calibration_status(dsi);
2524         }
2525
2526         clk_disable_unprepare(clk72mhz);
2527 }
2528 #endif
2529
2530 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2531 void tegra_dsi_mipi_calibration_14x(struct tegra_dc_dsi_data *dsi)
2532 {
2533         u32 val;
2534         struct clk *clk72mhz = NULL;
2535
2536         clk72mhz = clk_get_sys("clk72mhz", NULL);
2537         if (IS_ERR_OR_NULL(clk72mhz)) {
2538                 dev_err(&dsi->dc->ndev->dev, "dsi: can't get clk72mhz clock\n");
2539                 return;
2540         }
2541         clk_prepare_enable(clk72mhz);
2542
2543         tegra_mipi_cal_write(dsi->mipi_cal,
2544                         PAD_DRIV_DN_REF(0x2),
2545                         MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
2546
2547         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2548                      DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1));
2549         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2550
2551         val = (DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
2552         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
2553
2554         val = MIPI_CAL_HSCLKPDOSDSIA(0x2) |
2555                 MIPI_CAL_HSCLKPUOSDSIA(0x2);
2556         tegra_mipi_cal_write(dsi->mipi_cal, val,
2557                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2_0);
2558         tegra_mipi_cal_write(dsi->mipi_cal, val,
2559                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2_0);
2560
2561         val = MIPI_CAL_OVERIDEDSIA(0x0) |
2562                 MIPI_CAL_SELDSIA(0x1) |
2563                 MIPI_CAL_HSPDOSDSIA(0x0) |
2564                 MIPI_CAL_HSPUOSDSIA(0x0) |
2565                 MIPI_CAL_TERMOSDSIA(0x0);
2566         tegra_mipi_cal_write(dsi->mipi_cal, val,
2567                 MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2568         tegra_mipi_cal_write(dsi->mipi_cal, val,
2569                 MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2570
2571         val = MIPI_CAL_NOISE_FLT(0xa) |
2572                   MIPI_CAL_PRESCALE(0x2) |
2573                   MIPI_CAL_CLKEN_OVR(0x1) |
2574                   MIPI_CAL_AUTOCAL_EN(0x0);
2575         tegra_mipi_cal_write(dsi->mipi_cal, val,
2576                 MIPI_CAL_MIPI_CAL_CTRL_0);
2577
2578         tegra_dsi_mipi_calibration_status(dsi);
2579
2580         clk_disable_unprepare(clk72mhz);
2581 }
2582 #endif
2583
2584 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2585 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2586 {
2587         u32 val;
2588         /* Calibration settings begin */
2589         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2590                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2591                 DSI_PAD_OUTADJCLK(0x0));
2592         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2593
2594         /* Calibrate DSI 0 */
2595         if (dsi->info.ganged_type ||
2596                 dsi->info.dsi_instance == DSI_INSTANCE_0) {
2597                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2598                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2599                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2600                         MIPI_CAL_SELDSIA(0x1) |
2601                         MIPI_CAL_HSPDOSDSIA(0x0) |
2602                         MIPI_CAL_HSPUOSDSIA(0x4) |
2603                         MIPI_CAL_TERMOSDSIA(0x5);
2604                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2605                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2606                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2607                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2608
2609                 /* Deselect PAD C */
2610                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2611                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2612                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2613                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2614                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2615
2616                 /* Deselect PAD D */
2617                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2618                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2619                 val &= ~(MIPI_CAL_SELDSID(0x1));
2620                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2621                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2622
2623                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2624                         MIPI_CAL_MIPI_CAL_CTRL_0);
2625                 val = MIPI_CAL_NOISE_FLT(0xa) |
2626                           MIPI_CAL_PRESCALE(0x2) |
2627                           MIPI_CAL_CLKEN_OVR(0x1) |
2628                           MIPI_CAL_AUTOCAL_EN(0x0);
2629                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2630                         MIPI_CAL_MIPI_CAL_CTRL_0);
2631
2632                 tegra_dsi_mipi_calibration_status(dsi);
2633         }
2634
2635         /* Calibrate DSI 1 */
2636         if (dsi->info.ganged_type ||
2637                 dsi->info.dsi_instance == DSI_INSTANCE_1) {
2638                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2639                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2640                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2641                         MIPI_CAL_SELDSIC(0x1) |
2642                         MIPI_CAL_HSPDOSDSIC(0x0) |
2643                         MIPI_CAL_HSPUOSDSIC(0x4) |
2644                         MIPI_CAL_TERMOSDSIC(0x5);
2645                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2646                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2647                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2648                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2649
2650                 /* Deselect PAD A */
2651                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2652                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2653                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2654                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2655                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2656
2657                 /* Deselect PAD B */
2658                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2659                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2660                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2661                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2662                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2663
2664                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2665                         MIPI_CAL_MIPI_CAL_CTRL_0);
2666                 val = MIPI_CAL_NOISE_FLT(0xa) |
2667                           MIPI_CAL_PRESCALE(0x2) |
2668                           MIPI_CAL_CLKEN_OVR(0x1) |
2669                           MIPI_CAL_AUTOCAL_EN(0x0);
2670                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2671                         MIPI_CAL_MIPI_CAL_CTRL_0);
2672
2673                 tegra_dsi_mipi_calibration_status(dsi);
2674         }
2675 }
2676 #endif
2677 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2678 {
2679         u32 val = 0, reg;
2680
2681         if (!dsi->ulpm)
2682                 tegra_dsi_pad_enable(dsi);
2683         else
2684                 tegra_dsi_pad_disable(dsi);
2685
2686         if (dsi->info.controller_vs == DSI_VS_1) {
2687
2688                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2689
2690                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2691
2692                 /* Deselect CSI pads */
2693                 for (reg = MIPI_CAL_CILA_MIPI_CAL_CONFIG_0;
2694                         reg <= MIPI_CAL_CILF_MIPI_CAL_CONFIG_0;
2695                         reg += 4) {
2696                         val = tegra_mipi_cal_read(dsi->mipi_cal, reg);
2697                         val &= ~(MIPI_CAL_SELA(0x1));
2698                         tegra_mipi_cal_write(dsi->mipi_cal, val, reg);
2699                 }
2700
2701                 /* enable mipi bias pad */
2702                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2703                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2704                 val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
2705                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2706                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2707
2708 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
2709         defined(CONFIG_ARCH_TEGRA_14x_SOC) || \
2710         defined(CONFIG_ARCH_TEGRA_12x_SOC)
2711                 tegra_mipi_cal_write(dsi->mipi_cal,
2712                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2713                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2714 #else
2715                 tegra_mipi_cal_write(dsi->mipi_cal,
2716                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x0),
2717                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2718 #endif
2719                 tegra_mipi_cal_write(dsi->mipi_cal,
2720                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2721                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2722 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2723                 tegra_dsi_mipi_calibration_11x(dsi);
2724 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
2725                 tegra_dsi_mipi_calibration_14x(dsi);
2726 #elif defined(CONFIG_ARCH_TEGRA_13x_SOC)
2727                 tegra_dsi_mipi_calibration_13x(dsi);
2728 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2729                 tegra_dsi_mipi_calibration_12x(dsi);
2730 #elif defined(CONFIG_ARCH_TEGRA_21x_SOC)
2731                 tegra_dsi_mipi_calibration_21x(dsi);
2732 #endif
2733                 /* disable mipi bias pad */
2734                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2735                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2736                 val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
2737                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2738                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2739
2740                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2741         } else {
2742 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2743                 u32 val = 0;
2744
2745                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2746                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2747                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2748                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2749                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2750                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2751
2752                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2753                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2754                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2755                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2756                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2757
2758                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2759
2760                 val = MIPI_CAL_TERMOSA(0x4);
2761                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2762
2763                 val = MIPI_CAL_TERMOSB(0x4);
2764                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2765
2766                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2767                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2768
2769                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2770                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2771
2772                 val = PAD_CIL_PDVREG(0x0);
2773                 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2774 #endif
2775         }
2776 }
2777
2778 static void tegra_dsi_panelB_enable(void)
2779 {
2780         unsigned int val;
2781
2782         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2783         val |= DSIB_MODE_ENABLE;
2784         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2785 }
2786
2787 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2788                                 struct tegra_dc_dsi_data *dsi)
2789 {
2790         u32 i;
2791         int err = 0;
2792
2793         if (dsi->avdd_dsi_csi)
2794                 err = regulator_enable(dsi->avdd_dsi_csi);
2795         if (WARN(err, "unable to enable regulator"))
2796                 return err;
2797         /* stablization delay */
2798         mdelay(50);
2799         /* Enable DSI clocks */
2800         tegra_dsi_clk_enable(dsi);
2801         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2802
2803         /* Stop DC stream before configuring DSI registers
2804          * to avoid visible glitches on panel during transition
2805          * from bootloader to kernel driver
2806          */
2807         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2808
2809         tegra_dsi_writel(dsi,
2810                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2811                 DSI_POWER_CONTROL);
2812         /* stabilization delay */
2813         udelay(300);
2814
2815         if (dsi->info.dsi_instance || dsi->info.ganged_type)
2816                 tegra_dsi_panelB_enable();
2817
2818         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2819
2820         /* Initialize DSI registers */
2821         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2822                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2823         if (dsi->info.controller_vs == DSI_VS_1) {
2824                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2825                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2826         }
2827
2828 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2829         if (tegra_platform_is_fpga()) {
2830                 if (dsi->info.video_data_type ==
2831                                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
2832                         /* HW fpga WAR: dsi byte clk to dsi pixel clk ratio */
2833                         tegra_dsi_writel(dsi, 0x8, DSI_INIT_SEQ_DATA_15);
2834                 }
2835         }
2836 #endif
2837
2838         tegra_dsi_pad_calibration(dsi);
2839
2840         tegra_dsi_writel(dsi,
2841                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2842                 DSI_POWER_CONTROL);
2843         /* stabilization delay */
2844         udelay(300);
2845
2846         dsi->status.init = DSI_MODULE_INIT;
2847         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2848         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2849         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2850         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2851         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2852         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2853         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2854         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2855
2856         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
2857                 tegra_dsi_syncpt_reset(dsi);
2858
2859         return 0;
2860 }
2861
2862 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2863                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2864 {
2865         int err;
2866
2867         if (dsi->status.init != DSI_MODULE_INIT) {
2868                 err = -EPERM;
2869                 goto fail;
2870         }
2871
2872         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2873                         dsi->status.lp_op == lp_op)
2874                 goto success;
2875
2876         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2877                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2878
2879         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2880         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2881                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2882                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2883
2884         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2885         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2886                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2887                 tegra_dsi_set_timeout(dsi);
2888         }
2889
2890         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2891
2892         tegra_dsi_set_control_reg_lp(dsi);
2893
2894         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2895                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2896                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2897
2898         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2899         dsi->status.lp_op = lp_op;
2900         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2901 success:
2902         err = 0;
2903 fail:
2904         return err;
2905 }
2906
2907 static void tegra_dsi_ganged(struct tegra_dc *dc,
2908                                 struct tegra_dc_dsi_data *dsi)
2909 {
2910         u32 low_width = 0;
2911         u32 high_width = 0;
2912         u32 h_active = dc->out->modes->h_active;
2913         u32 val = 0;
2914         int dsi_instances[2];
2915         u16 ganged_pointer = DIV_ROUND_UP(h_active, 2);
2916
2917         if (dsi->info.controller_vs < DSI_VS_1) {
2918                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2919                 "supported with current controller version\n");
2920                 return;
2921         }
2922
2923         if (dsi->info.ganged_swap_links) {
2924                 dsi_instances[0] = DSI_INSTANCE_1;
2925                 dsi_instances[1] = DSI_INSTANCE_0;
2926         } else {
2927                 dsi_instances[0] = DSI_INSTANCE_0;
2928                 dsi_instances[1] = DSI_INSTANCE_1;
2929         }
2930
2931         if (dsi->info.ganged_type ==
2932                 TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP &&
2933                 dsi->info.ganged_overlap)
2934                 ganged_pointer -= dsi->info.ganged_overlap;
2935
2936         if (dsi->info.ganged_type ==
2937                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
2938                 dsi->info.ganged_type ==
2939                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP) {
2940                 /* DSI 0 */
2941                 tegra_dsi_controller_writel(dsi,
2942                         DSI_GANGED_MODE_START_POINTER(0),
2943                         DSI_GANGED_MODE_START, dsi_instances[0]);
2944                 /* DSI 1 */
2945                 tegra_dsi_controller_writel(dsi,
2946                         DSI_GANGED_MODE_START_POINTER(ganged_pointer),
2947                         DSI_GANGED_MODE_START, dsi_instances[1]);
2948
2949                 low_width = ganged_pointer;
2950                 high_width = h_active - low_width;
2951                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2952                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2953
2954         } else if (dsi->info.ganged_type ==
2955                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2956                 /* DSI 0 */
2957                 tegra_dsi_controller_writel(dsi,
2958                         DSI_GANGED_MODE_START_POINTER(0),
2959                         DSI_GANGED_MODE_START, dsi_instances[0]);
2960                 /* DSI 1 */
2961                 tegra_dsi_controller_writel(dsi,
2962                         DSI_GANGED_MODE_START_POINTER(
2963                                 dsi->info.even_odd_split_width),
2964                         DSI_GANGED_MODE_START, dsi_instances[1]);
2965
2966                 low_width = dsi->info.even_odd_split_width;
2967                 high_width = dsi->info.even_odd_split_width;
2968                 val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2969                         DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2970         }
2971
2972         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2973
2974         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2975                                                 DSI_GANGED_MODE_CONTROL);
2976 }
2977
2978 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2979                                         struct tegra_dc_dsi_data *dsi,
2980                                         u8 driven_mode)
2981 {
2982         int err;
2983
2984         if (dsi->status.init != DSI_MODULE_INIT) {
2985                 err = -EPERM;
2986                 goto fail;
2987         }
2988
2989         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2990                 dsi->driven_mode == driven_mode)
2991                 goto success;
2992
2993         dsi->driven_mode = driven_mode;
2994
2995         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2996                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2997
2998         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2999                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
3000                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3001
3002         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
3003                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
3004                 tegra_dsi_set_timeout(dsi);
3005         }
3006
3007         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
3008
3009         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
3010                 tegra_dsi_set_pkt_seq(dc, dsi);
3011                 tegra_dsi_set_pkt_length(dc, dsi);
3012                 tegra_dsi_set_sol_delay(dc, dsi);
3013                 tegra_dsi_set_dc_clk(dc, dsi);
3014         }
3015
3016         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
3017
3018         if (dsi->info.ganged_type)
3019                 tegra_dsi_ganged(dc, dsi);
3020
3021         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
3022                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
3023                 tegra_dsi_hs_clk_out_enable(dsi);
3024
3025         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3026 success:
3027         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3028         err = 0;
3029 fail:
3030         return err;
3031 }
3032
3033 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3034 {
3035         u32 timeout = 0;
3036         bool retVal = true;
3037
3038         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
3039                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
3040                         tegra_dsi_controller_readl(dsi,
3041                                         DSI_TRIGGER, link_id))) {
3042                         retVal = false;
3043                         break;
3044                 }
3045                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
3046                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
3047         }
3048
3049         return retVal;
3050 }
3051
3052 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3053 {
3054         u32 timeout = 0;
3055         bool retVal = true;
3056
3057         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
3058                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
3059                         tegra_dsi_controller_readl(dsi,
3060                                         DSI_HOST_DSI_CONTROL, link_id))) {
3061                         retVal = false;
3062                         break;
3063                 }
3064                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
3065                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
3066         }
3067
3068         return retVal;
3069 }
3070
3071 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi, u8 link_id)
3072 {
3073         int err = 0;
3074
3075         if (tegra_dsi_write_busy(dsi, link_id)) {
3076                 err = -EBUSY;
3077                 dev_err(&dsi->dc->ndev->dev,
3078                         "DSI trigger bit already set\n");
3079                 goto fail;
3080         }
3081
3082         if (tegra_dsi_read_busy(dsi, link_id)) {
3083                 err = -EBUSY;
3084                 dev_err(&dsi->dc->ndev->dev,
3085                         "DSI immediate bta bit already set\n");
3086                 goto fail;
3087         }
3088 fail:
3089         return (err < 0 ? true : false);
3090 }
3091
3092 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
3093 {
3094         u32 val;
3095
3096         val = tegra_dsi_readl(dsi, DSI_STATUS);
3097         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3098         if (val) {
3099                 dev_warn(&dsi->dc->ndev->dev,
3100                         "DSI read count not zero, resetting\n");
3101                 tegra_dsi_soft_reset(dsi);
3102         }
3103 }
3104
3105 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
3106                                                 struct tegra_dc_dsi_data *dsi,
3107                                                 struct tegra_dc *dc,
3108                                                 u8 lp_op)
3109 {
3110         struct dsi_status *init_status = NULL;
3111         int err;
3112
3113         if (dsi->status.init != DSI_MODULE_INIT ||
3114                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
3115                 err = -EPERM;
3116                 goto fail;
3117         }
3118
3119         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
3120         if (!init_status)
3121                 return ERR_PTR(-ENOMEM);
3122
3123         *init_status = dsi->status;
3124
3125         if (dsi->info.hs_cmd_mode_supported) {
3126                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3127                                 TEGRA_DSI_DRIVEN_BY_HOST);
3128                 if (err < 0) {
3129                         dev_err(&dc->ndev->dev,
3130                         "Switch to HS host mode failed\n");
3131                         goto fail;
3132                 }
3133
3134                 goto success;
3135         }
3136
3137         if (dsi->status.lp_op != lp_op) {
3138                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3139                 if (err < 0) {
3140                         dev_err(&dc->ndev->dev,
3141                         "DSI failed to go to LP mode\n");
3142                         goto fail;
3143                 }
3144         }
3145 success:
3146         return init_status;
3147 fail:
3148         kfree(init_status);
3149         return ERR_PTR(err);
3150 }
3151
3152 static struct dsi_status *tegra_dsi_prepare_host_transmission(
3153                                 struct tegra_dc *dc,
3154                                 struct tegra_dc_dsi_data *dsi,
3155                                 u8 lp_op)
3156 {
3157         int i = 0;
3158         int err = 0;
3159         struct dsi_status *init_status;
3160         bool restart_dc_stream = false;
3161
3162         if (dsi->status.init != DSI_MODULE_INIT ||
3163                 dsi->ulpm) {
3164                 err = -EPERM;
3165                 goto fail;
3166         }
3167
3168         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
3169                 restart_dc_stream = true;
3170                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3171         }
3172
3173         for (i = 0; i < dsi->max_instances; i++) {
3174                 if (tegra_dsi_host_busy(dsi, i)) {
3175                         tegra_dsi_soft_reset(dsi);
3176                         if (tegra_dsi_host_busy(dsi, i)) {
3177                                 err = -EBUSY;
3178                                 dev_err(&dc->ndev->dev, "DSI host busy\n");
3179                                 goto fail;
3180                         }
3181                 }
3182         }
3183
3184         if (lp_op == DSI_LP_OP_READ)
3185                 tegra_dsi_reset_read_count(dsi);
3186
3187         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
3188                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3189                 if (err < 0) {
3190                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
3191                         goto fail;
3192                 }
3193         }
3194
3195         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
3196                                         (dsi, dc, lp_op);
3197         if (IS_ERR_OR_NULL(init_status)) {
3198                 err = PTR_ERR(init_status);
3199                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
3200                 goto fail;
3201         }
3202
3203         if (restart_dc_stream)
3204                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
3205
3206         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3207                 if (atomic_read(&dsi_syncpt_rst))
3208                         tegra_dsi_syncpt_reset(dsi);
3209
3210         return init_status;
3211 fail:
3212         return ERR_PTR(err);
3213 }
3214
3215 static int tegra_dsi_restore_state(struct tegra_dc *dc,
3216                                 struct tegra_dc_dsi_data *dsi,
3217                                 struct dsi_status *init_status)
3218 {
3219         int err = 0;
3220
3221         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
3222                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
3223                 if (err < 0) {
3224                         dev_err(&dc->ndev->dev,
3225                                 "Failed to config LP mode\n");
3226                         goto fail;
3227                 }
3228                 goto success;
3229         }
3230
3231         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
3232                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
3233                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
3234                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
3235                 if (err < 0) {
3236                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
3237                         goto fail;
3238                 }
3239         }
3240
3241         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
3242                 tegra_dsi_start_dc_stream(dc, dsi);
3243 success:
3244 fail:
3245         kfree(init_status);
3246         return err;
3247 }
3248
3249 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi, u8 link_id)
3250 {
3251         int status = 0;
3252
3253         if (tegra_dsi_controller_readl(dsi, DSI_TRIGGER, link_id)) {
3254                 status = -EBUSY;
3255                 goto fail;
3256         }
3257
3258         tegra_dsi_controller_writel(dsi,
3259                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE),
3260                                 DSI_TRIGGER, link_id);
3261
3262         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3263                 status = tegra_dsi_syncpt(dsi, link_id);
3264                 if (status < 0) {
3265                         dev_err(&dsi->dc->ndev->dev,
3266                                 "DSI syncpt for host trigger failed\n");
3267                         goto fail;
3268                 }
3269         } else {
3270                 if (tegra_dsi_write_busy(dsi, link_id)) {
3271                         status = -EBUSY;
3272                         dev_err(&dsi->dc->ndev->dev,
3273                                 "Timeout waiting on write completion\n");
3274                 }
3275         }
3276
3277 fail:
3278         return status;
3279 }
3280
3281 static int _tegra_dsi_controller_write_data(struct tegra_dc_dsi_data *dsi,
3282                                         struct tegra_dsi_cmd *cmd, int link_id)
3283 {
3284         u8 virtual_channel;
3285         u32 val;
3286         int err;
3287         u8 *pdata = cmd->pdata;
3288         u8 data_id = cmd->data_id;
3289         u16 data_len = cmd->sp_len_dly.data_len;
3290
3291         err = 0;
3292
3293         if (!dsi->info.ganged_type && link_id == TEGRA_DSI_LINK1) {
3294                 dev_err(&dsi->dc->ndev->dev, "DSI invalid command\n");
3295                 return -EINVAL;
3296         }
3297
3298         virtual_channel = dsi->info.virtual_channel <<
3299                                                 DSI_VIR_CHANNEL_BIT_POSITION;
3300
3301         /* always use hw for ecc */
3302         val = (virtual_channel | data_id) << 0 |
3303                         data_len << 8;
3304         tegra_dsi_controller_writel(dsi, val, DSI_WR_DATA, link_id);
3305
3306         /* if pdata != NULL, pkt type is long pkt */
3307         if (pdata != NULL) {
3308                 while (data_len) {
3309                         if (data_len >= 4) {
3310                                 val = ((u32 *) pdata)[0];
3311                                 data_len -= 4;
3312                                 pdata += 4;
3313                         } else {
3314                                 val = 0;
3315                                 memcpy(&val, pdata, data_len);
3316                                 pdata += data_len;
3317                                 data_len = 0;
3318                         }
3319                         tegra_dsi_controller_writel(dsi, val,
3320                                 DSI_WR_DATA, link_id);
3321                 }
3322         }
3323
3324         if (cmd->cmd_type != TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3325                 err = tegra_dsi_host_trigger(dsi, link_id);
3326                 if (err < 0)
3327                         dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
3328         }
3329
3330         return err;
3331 }
3332
3333 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
3334                                         struct tegra_dsi_cmd *cmd)
3335 {
3336         int i, err = 0;
3337
3338         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
3339                 for (i = 0; i < dsi->max_instances; i++) {
3340                         err = _tegra_dsi_controller_write_data(dsi, cmd, i);
3341                         if (err)
3342                                 break;
3343                 }
3344         else
3345                 err = _tegra_dsi_controller_write_data(dsi, cmd, cmd->link_id);
3346
3347         return err;
3348 }
3349
3350 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
3351 {
3352         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3353
3354         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3355                 atomic_inc(&dsi->host_ref);
3356                 tegra_dsi_host_resume(dc);
3357         }
3358 }
3359
3360 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
3361 {
3362         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3363
3364         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
3365                 atomic_dec(&dsi->host_ref);
3366
3367                 if (!atomic_read(&dsi->host_ref) &&
3368                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
3369                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
3370         }
3371 }
3372
3373 static void tegra_dc_dsi_idle_work(struct work_struct *work)
3374 {
3375         struct tegra_dc_dsi_data *dsi = container_of(
3376                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
3377
3378         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
3379                 tegra_dsi_host_suspend(dsi->dc);
3380 }
3381
3382 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
3383                         struct tegra_dc_dsi_data *dsi,
3384                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3385 {
3386         int err = 0;
3387         int restore_err = 0;
3388         struct dsi_status *init_status;
3389
3390         init_status = tegra_dsi_prepare_host_transmission(
3391                                 dc, dsi, DSI_LP_OP_WRITE);
3392         if (IS_ERR_OR_NULL(init_status)) {
3393                 err = PTR_ERR(init_status);
3394                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3395                 goto fail;
3396         }
3397
3398         err = _tegra_dsi_write_data(dsi, cmd);
3399         if (err < 0) {
3400                 dev_err(&dc->ndev->dev, "Failed DSI write\n");
3401                 restore_err = tegra_dsi_restore_state(dc, dsi, init_status);
3402                 if (restore_err < 0)
3403                         dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3404                 goto fail;
3405         }
3406
3407         mdelay(delay_ms);
3408
3409         err = tegra_dsi_restore_state(dc, dsi, init_status);
3410         if (err < 0)
3411                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3412
3413 fail:
3414         return err;
3415 }
3416
3417 int tegra_dsi_write_data(struct tegra_dc *dc,
3418                         struct tegra_dc_dsi_data *dsi,
3419                         struct tegra_dsi_cmd *cmd, u8 delay_ms)
3420 {
3421         int err;
3422
3423         tegra_dc_io_start(dc);
3424         tegra_dc_dsi_hold_host(dc);
3425
3426         err = tegra_dsi_write_data_nosync(dc, dsi, cmd, delay_ms);
3427
3428         tegra_dc_dsi_release_host(dc);
3429         tegra_dc_io_end(dc);
3430
3431         return err;
3432 }
3433
3434 EXPORT_SYMBOL(tegra_dsi_write_data);
3435
3436 int tegra_dsi_start_host_cmd_v_blank_video(struct tegra_dc_dsi_data *dsi,
3437                                 struct tegra_dsi_cmd *cmd, u8 clubbed_cmd_no)
3438 {
3439         struct tegra_dc *dc = dsi->dc;
3440         int err = 0;
3441         u32 val;
3442         u8 i;
3443
3444         if (!dsi->enabled) {
3445                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3446                 return -EINVAL;
3447         }
3448
3449         tegra_dc_io_start(dc);
3450         tegra_dc_dsi_hold_host(dc);
3451
3452         val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3453         tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3454         if (clubbed_cmd_no)
3455                 for (i = 0; i < clubbed_cmd_no; i++)
3456                         _tegra_dsi_write_data(dsi, &cmd[i]);
3457         else
3458                 _tegra_dsi_write_data(dsi, &cmd[0]);
3459
3460         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3461                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3462                                 TEGRA_DSI_DRIVEN_BY_DC);
3463                 if (err < 0) {
3464                         dev_err(&dc->ndev->dev,
3465                                 "dsi: not able to set to hs mode\n");
3466                         goto fail;
3467                 }
3468         }
3469
3470         tegra_dsi_start_dc_stream(dc, dsi);
3471         tegra_dsi_wait_frame_end(dc, dsi, 2);
3472 fail:
3473         tegra_dc_dsi_release_host(dc);
3474         tegra_dc_io_end(dc);
3475
3476         return err;
3477 }
3478 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_video);
3479
3480 int tegra_dsi_end_host_cmd_v_blank_video(struct tegra_dc *dc,
3481                                         struct tegra_dc_dsi_data *dsi)
3482 {
3483         if (!dsi->enabled) {
3484                 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3485                 return -EINVAL;
3486         }
3487
3488         tegra_dc_io_start(dc);
3489         tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3490         tegra_dc_io_end(dc);
3491
3492         return 0;
3493 }
3494 EXPORT_SYMBOL(tegra_dsi_end_host_cmd_v_blank_video);
3495
3496 int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3497                                         struct tegra_dc_dsi_data *dsi,
3498                                         struct tegra_dsi_cmd *cmd,
3499                                         u32 n_cmd)
3500 {
3501 #define DEFAULT_DELAY_MS 1
3502         u32 i;
3503         int err;
3504         u8 delay_ms;
3505         int retry_count;
3506
3507         err = 0;
3508         for (i = 0; i < n_cmd; i++) {
3509                 struct tegra_dsi_cmd *cur_cmd;
3510                 cur_cmd = &cmd[i];
3511
3512                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
3513                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
3514                                        cur_cmd->data_id);
3515                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
3516                         usleep_range(cur_cmd->sp_len_dly.delay_ms * 1000,
3517                                 (cur_cmd->sp_len_dly.delay_ms * 1000) + 500);
3518                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
3519                                 tegra_dsi_send_dc_frames(dc,
3520                                                 dsi,
3521                                                 cur_cmd->sp_len_dly.frame_cnt);
3522                 } else if (cur_cmd->cmd_type ==
3523                                         TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3524                         u32 j;
3525                         for (j = i; j < n_cmd; j++) {
3526                                 if (!IS_DSI_SHORT_PKT(cmd[j]))
3527                                         break;
3528                                 if (cmd[j].club_cmd != CMD_CLUBBED)
3529                                         break;
3530                                 if (j - i + 1 > DSI_HOST_FIFO_DEPTH)
3531                                         break;
3532                         }
3533                         /* i..j-1: clubbable streak */
3534                         tegra_dsi_start_host_cmd_v_blank_video(dsi, cur_cmd,
3535                                                                         j - i);
3536                         tegra_dsi_end_host_cmd_v_blank_video(dc, dsi);
3537                         if (j != i)
3538                                 i = j - 1;
3539                 } else {
3540                         delay_ms = DEFAULT_DELAY_MS;
3541                         if ((i + 1 < n_cmd) &&
3542                                 (cmd[i + 1].cmd_type == TEGRA_DSI_DELAY_MS)) {
3543                                 delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
3544                                 i++;
3545                         }
3546                         retry_count = DSI_WRITE_DATA_RETRY_ATTEMPTS;
3547                         do {
3548                                 err = tegra_dsi_write_data_nosync(dc, dsi,
3549                                                         cur_cmd, delay_ms);
3550                                 if (err < 0) {
3551                                         retry_count--;
3552                                         dev_err(&dsi->dc->ndev->dev,
3553                                                 "dsi: %s failed, retrying...\n",__func__);
3554                                 } else {
3555                                         retry_count = 0;
3556                                 }
3557                         } while (retry_count);
3558                 }
3559         }
3560         return err;
3561 #undef DEFAULT_DELAY_MS
3562 }
3563
3564 static u8 tegra_dsi_ecc(u32 header)
3565 {
3566         char ecc_parity[24] = {
3567                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
3568                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
3569                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
3570         };
3571         u8 ecc_byte;
3572         int i;
3573
3574         ecc_byte = 0;
3575         for (i = 0; i < 24; i++)
3576                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
3577
3578         return ecc_byte;
3579 }
3580
3581 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
3582 {
3583         u16 byte_cnt;
3584         u8 bit_cnt;
3585         char curr_byte;
3586         u16 crc = 0xFFFF;
3587         u16 poly = 0x8408;
3588
3589         if (data_len > 0) {
3590                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
3591                         curr_byte = pdata[byte_cnt];
3592                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
3593                                 if (((crc & 0x0001) ^
3594                                         (curr_byte & 0x0001)) > 0)
3595                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
3596                                 else
3597                                         crc = (crc >> 1) & 0x7FFF;
3598
3599                                 curr_byte = (curr_byte >> 1) & 0x7F;
3600                         }
3601                 }
3602         }
3603         return crc;
3604 }
3605
3606 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
3607                                                 struct tegra_dsi_cmd *cmd)
3608 {
3609         u8 virtual_channel;
3610         u32 val;
3611         u16 data_len = cmd->sp_len_dly.data_len;
3612         u8 seq_ctrl_reg = 0;
3613
3614         virtual_channel = dsi->info.virtual_channel <<
3615                                 DSI_VIR_CHANNEL_BIT_POSITION;
3616
3617         val = (virtual_channel | cmd->data_id) << 0 |
3618                 data_len << 8;
3619
3620         val |= tegra_dsi_ecc(val) << 24;
3621
3622         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
3623
3624         /* if pdata != NULL, pkt type is long pkt */
3625         if (cmd->pdata != NULL) {
3626                 u8 *pdata;
3627                 u8 *pdata_mem;
3628                 /* allocate memory for pdata + 2 bytes checksum */
3629                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
3630                 if (!pdata_mem) {
3631                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
3632                         tegra_dsi_soft_reset(dsi);
3633                         return -ENOMEM;
3634                 }
3635
3636                 memcpy(pdata_mem, cmd->pdata, data_len);
3637                 pdata = pdata_mem;
3638                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
3639
3640                 /* data_len = length of pdata + 2 byte checksum */
3641                 data_len += 2;
3642
3643                 while (data_len) {
3644                         if (data_len >= 4) {
3645                                 val = ((u32 *) pdata)[0];
3646                                 data_len -= 4;
3647                                 pdata += 4;
3648                         } else {
3649                                 val = 0;
3650                                 memcpy(&val, pdata, data_len);
3651                                 pdata += data_len;
3652                                 data_len = 0;
3653                         }
3654                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
3655                                                         seq_ctrl_reg++);
3656                 }
3657                 kfree(pdata_mem);
3658         }
3659
3660         return 0;
3661 }
3662
3663 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
3664                                                 struct tegra_dsi_cmd *cmd)
3665 {
3666 #define PKT_HEADER_LEN_BYTE     4
3667 #define CHECKSUM_LEN_BYTE       2
3668
3669         int err = 0;
3670         u32 val;
3671         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
3672         struct tegra_dc *dc = dsi->dc;
3673
3674         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
3675                 return -EINVAL;
3676
3677         mutex_lock(&dsi->lock);
3678         tegra_dc_io_start(dc);
3679         tegra_dc_dsi_hold_host(dc);
3680
3681 #if DSI_USE_SYNC_POINTS
3682         atomic_set(&dsi_syncpt_rst, 1);
3683 #endif
3684
3685         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
3686         if (err < 0) {
3687                 dev_err(&dsi->dc->ndev->dev,
3688                         "dsi: dcs pkt seq ctrl init failed\n");
3689                 goto fail;
3690         }
3691
3692         if (cmd->pdata) {
3693                 u16 data_len = cmd->sp_len_dly.data_len;
3694                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
3695         }
3696
3697         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
3698                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
3699                                                 TEGRA_DSI_ENABLE);
3700         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
3701
3702 fail:
3703         tegra_dc_dsi_release_host(dc);
3704         tegra_dc_io_end(dc);
3705         mutex_unlock(&dsi->lock);
3706         return err;
3707
3708 #undef PKT_HEADER_LEN_BYTE
3709 #undef CHECKSUM_LEN_BYTE
3710 }
3711 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
3712
3713 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi)
3714 {
3715         struct tegra_dc *dc = dsi->dc;
3716         u32 cnt;
3717
3718         mutex_lock(&dsi->lock);
3719         tegra_dc_io_start(dc);
3720         tegra_dc_dsi_hold_host(dc);
3721
3722         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3723                 if (atomic_read(&dsi_syncpt_rst)) {
3724                         tegra_dsi_wait_frame_end(dc, dsi, 2);
3725                         tegra_dsi_syncpt_reset(dsi);
3726                         atomic_set(&dsi_syncpt_rst, 0);
3727                 }
3728
3729         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
3730
3731         /* clear seq data registers */
3732         for (cnt = 0; cnt < 8; cnt++)
3733                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
3734
3735         tegra_dc_dsi_release_host(dc);
3736         tegra_dc_io_end(dc);
3737
3738         mutex_unlock(&dsi->lock);
3739 }
3740 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
3741
3742 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3743 {
3744         u32 val;
3745         int err = 0;
3746
3747         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3748         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
3749
3750         if (dsi->info.ganged_type && dsi->info.ganged_write_to_all_links)
3751                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3752         else
3753                 tegra_dsi_controller_writel(dsi, val,
3754                                 DSI_HOST_DSI_CONTROL, TEGRA_DSI_LINK0);
3755
3756         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
3757                 err = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
3758                 if (err < 0) {
3759                         dev_err(&dsi->dc->ndev->dev,
3760                                 "DSI syncpt for bta failed\n");
3761                 }
3762         } else {
3763                 if (tegra_dsi_read_busy(dsi, TEGRA_DSI_LINK0)) {
3764                         err = -EBUSY;
3765                         dev_err(&dsi->dc->ndev->dev,
3766                                 "Timeout wating on read completion\n");
3767                 }
3768         }
3769
3770         return err;
3771 }
3772
3773 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
3774                                         u32 rd_fifo_cnt, u8 *read_fifo)
3775 {
3776         int err;
3777         u32 payload_size;
3778
3779         payload_size = 0;
3780         err = 0;
3781
3782         switch (read_fifo[0]) {
3783         case DSI_ESCAPE_CMD:
3784                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
3785                 break;
3786         case DSI_ACK_NO_ERR:
3787                 dev_info(&dc->ndev->dev,
3788                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
3789                 return err;
3790         default:
3791                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3792                 break;
3793         }
3794
3795         switch (read_fifo[4] & 0xff) {
3796         case GEN_LONG_RD_RES:
3797                 /* Fall through */
3798         case DCS_LONG_RD_RES:
3799                 payload_size = (read_fifo[5] |
3800                                 (read_fifo[6] << 8)) & 0xFFFF;
3801                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3802                                 "payload_size[0x%x]\n", payload_size);
3803                 break;
3804         case GEN_1_BYTE_SHORT_RD_RES:
3805                 /* Fall through */
3806         case DCS_1_BYTE_SHORT_RD_RES:
3807                 payload_size = 1;
3808                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3809                         "payload_size[0x%x]\n", payload_size);
3810                 break;
3811         case GEN_2_BYTE_SHORT_RD_RES:
3812                 /* Fall through */
3813         case DCS_2_BYTE_SHORT_RD_RES:
3814                 payload_size = 2;
3815                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3816                         "payload_size[0x%x]\n", payload_size);
3817                 break;
3818         case ACK_ERR_RES:
3819                 payload_size = 2;
3820                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3821                         "Packet payload_size[0x%x]\n", payload_size);
3822                 break;
3823         default:
3824                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3825                 err = -EINVAL;
3826                 break;
3827         }
3828         return err;
3829 }
3830
3831 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3832                         struct tegra_dc_dsi_data *dsi,
3833                         u8 *read_fifo)
3834 {
3835         u32 val;
3836         u32 i;
3837         u32 poll_time = 0;
3838         u32 rd_fifo_cnt;
3839         int err = 0;
3840         u8 *read_fifo_cp = read_fifo;
3841
3842         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3843                 mdelay(1);
3844                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3845                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3846                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3847                         dev_err(&dc->ndev->dev,
3848                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3849                         break;
3850                 }
3851                 poll_time++;
3852         }
3853
3854         if (rd_fifo_cnt == 0) {
3855                 dev_info(&dc->ndev->dev,
3856                         "DSI RD_FIFO_CNT is zero\n");
3857                 err = -EINVAL;
3858                 goto fail;
3859         }
3860
3861         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3862                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3863                 dev_warn(&dc->ndev->dev,
3864                         "DSI overflow/underflow error\n");
3865         }
3866
3867         /* Read data from FIFO */
3868         for (i = 0; i < rd_fifo_cnt; i++) {
3869                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3870                 if (enable_read_debug)
3871                         dev_info(&dc->ndev->dev,
3872                         "Read data[%d]: 0x%x\n", i, val);
3873                 memcpy(read_fifo, &val, 4);
3874                 read_fifo += 4;
3875         }
3876
3877         /* Make sure all the data is read from the FIFO */
3878         val = tegra_dsi_readl(dsi, DSI_STATUS);
3879         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3880         if (val)
3881                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3882                 " even after reading FIFO_RD_CNT words from read fifo\n");
3883
3884         if (enable_read_debug) {
3885                 err =
3886                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3887                 if (err < 0)
3888                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3889         }
3890 fail:
3891         return err;
3892 }
3893
3894 int tegra_dsi_read_data(struct tegra_dc *dc,
3895                                 struct tegra_dc_dsi_data *dsi,
3896                                 u16 max_ret_payload_size,
3897                                 u8 panel_reg_addr, u8 *read_data)
3898 {
3899         int err = 0;
3900         struct dsi_status *init_status;
3901         static struct tegra_dsi_cmd temp_cmd;
3902
3903         if (!dsi->enabled) {
3904                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3905                 return -EINVAL;
3906         }
3907         tegra_dc_dsi_hold_host(dc);
3908         mutex_lock(&dsi->lock);
3909         tegra_dc_io_start(dc);
3910         clk_prepare_enable(dsi->dsi_fixed_clk);
3911         tegra_dsi_lp_clk_enable(dsi);
3912         init_status = tegra_dsi_prepare_host_transmission(
3913                                 dc, dsi, DSI_LP_OP_WRITE);
3914         if (IS_ERR_OR_NULL(init_status)) {
3915                 err = PTR_ERR(init_status);
3916                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3917                 goto fail;
3918         }
3919
3920         /* Set max return payload size in words */
3921         temp_cmd.data_id = dsi_command_max_return_pkt_size;
3922         temp_cmd.sp_len_dly.data_len = max_ret_payload_size;
3923         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3924         if (err < 0) {
3925                 dev_err(&dc->ndev->dev,
3926                                 "DSI write failed\n");
3927                 goto fail;
3928         }
3929
3930         /* DCS to read given panel register */
3931         temp_cmd.data_id = dsi_command_dcs_read_with_no_params;
3932         temp_cmd.sp_len_dly.sp.data0 = panel_reg_addr;
3933         temp_cmd.sp_len_dly.sp.data1 = 0;
3934         err = _tegra_dsi_write_data(dsi, &temp_cmd);
3935         if (err < 0) {
3936                 dev_err(&dc->ndev->dev,
3937                                 "DSI write failed\n");
3938                 goto fail;
3939         }
3940
3941         tegra_dsi_reset_read_count(dsi);
3942
3943         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3944                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3945                 if (err < 0) {
3946                         dev_err(&dc->ndev->dev,
3947                         "DSI failed to go to LP read mode\n");
3948                         goto fail;
3949                 }
3950         }
3951
3952         err = tegra_dsi_bta(dsi);
3953         if (err < 0) {
3954                 dev_err(&dc->ndev->dev,
3955                         "DSI IMM BTA timeout\n");
3956                 goto fail;
3957         }
3958
3959         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3960         if (err < 0) {
3961                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3962                 goto fail;
3963         }
3964 fail:
3965         err = tegra_dsi_restore_state(dc, dsi, init_status);
3966         if (err < 0)
3967                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3968         tegra_dsi_lp_clk_disable(dsi);
3969         clk_disable_unprepare(dsi->dsi_fixed_clk);
3970         tegra_dc_io_end(dc);
3971         mutex_unlock(&dsi->lock);
3972         tegra_dc_dsi_release_host(dc);
3973         return err;
3974 }
3975 EXPORT_SYMBOL(tegra_dsi_read_data);
3976
3977 static const char * const error_sanity[] = {
3978                 "SoT Error",
3979                 "SoT Sync Error",
3980                 "EoT Sync Error",
3981                 "Escape Mode Entry Comand Error",
3982                 "Low-Power Transmit Sync Error",
3983                 "HS Receive Timeout Error",
3984                 "False Control Error",
3985                 "Reserved",
3986                 "ECC Error,Single Bit",
3987                 "ECC Error, Multi Bit",
3988                 "Checksum Error",
3989                 "DSI Data Type Not recognized",
3990                 "DSI VC ID Invalid",
3991                 "DSI Protocol Violation",
3992                 "Reserved",
3993                 "Reserved",
3994 };
3995
3996 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3997                                 struct tegra_dc_dsi_data *dsi,
3998                                 struct sanity_status *san)
3999 {
4000         int err = 0;
4001         u32 flagset[16];
4002         u8 read_fifo[DSI_READ_FIFO_DEPTH];
4003         struct dsi_status *init_status;
4004         static struct tegra_dsi_cmd dsi_nop_cmd =
4005                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
4006
4007         if (!dsi->enabled) {
4008                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
4009                 return -EINVAL;
4010         }
4011         tegra_dc_dsi_hold_host(dc);
4012         tegra_dc_io_start(dc);
4013         clk_prepare_enable(dsi->dsi_fixed_clk);
4014         tegra_dsi_lp_clk_enable(dsi);
4015         memset(flagset, 0, sizeof(flagset));
4016         init_status = tegra_dsi_prepare_host_transmission(
4017                                 dc, dsi, DSI_LP_OP_WRITE);
4018         if (IS_ERR_OR_NULL(init_status)) {
4019                 err = PTR_ERR(init_status);
4020                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
4021                 goto fail;
4022         }
4023
4024         err = _tegra_dsi_write_data(dsi, &dsi_nop_cmd);
4025         if (err < 0) {
4026                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
4027                 goto fail;
4028         }
4029
4030         tegra_dsi_reset_read_count(dsi);
4031
4032         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
4033                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
4034                 if (err < 0) {
4035                         dev_err(&dc->ndev->dev,
4036                         "DSI failed to go to LP read mode\n");
4037                         goto fail;
4038                 }
4039         }
4040
4041         err = tegra_dsi_bta(dsi);
4042         if (err < 0) {
4043                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
4044                 goto fail;
4045         }
4046
4047         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
4048         if (err < 0) {
4049                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
4050                 goto fail;
4051         }
4052
4053         if (read_fifo[0] != DSI_ACK_NO_ERR) {
4054                 if (read_fifo[4] == ACK_ERR_RES) {
4055                         u16 payload = read_fifo[5] | (read_fifo[6] << 8);
4056                         int i = 0;
4057                         for (; payload; payload >>= 1, i++) {
4058                                 if (payload & 1) {
4059                                         flagset[i] = 0x01;
4060                                         if (enable_read_debug)
4061                                                 dev_info(&dc->ndev->dev,
4062                                                         " %s => error flag number %d\n",
4063                                                         error_sanity[i], i);
4064                                 }
4065                         }
4066                         if (san != NULL) {
4067                                 san->sot_error = flagset[0];
4068                                 san->sot_sync_error = flagset[1];
4069                                 san->eot_sync_error = flagset[2];
4070                                 san->escape_mode_entry_comand_error =
4071                                                 flagset[3];
4072                                 san->low_power_transmit_sync_error = flagset[4];
4073                                 san->hs_receive_timeout_error = flagset[5];
4074                                 san->false_control_error = flagset[6];
4075                                 san->reserved1 = flagset[7];
4076                                 san->ecc_error_single_bit = flagset[8];
4077                                 san->ecc_error_multi_bit = flagset[9];
4078                                 san->checksum_error = flagset[10];
4079                                 san->dsi_data_type_not_recognized = flagset[11];
4080                                 san->dsi_vc_id_invalid = flagset[12];
4081                                 san->dsi_protocol_violation = flagset[13];
4082                                 san->reserved2 = flagset[14];
4083                                 san->reserved3 = flagset[15];
4084                         }
4085                 }
4086                 dev_warn(&dc->ndev->dev,
4087                         "Ack no error trigger message not received\n");
4088                 err = -EAGAIN;
4089         }
4090
4091 fail:
4092         err = tegra_dsi_restore_state(dc, dsi, init_status);
4093         if (err < 0)
4094                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
4095         tegra_dsi_lp_clk_disable(dsi);
4096         clk_disable_unprepare(dsi->dsi_fixed_clk);
4097         tegra_dc_io_end(dc);
4098         tegra_dc_dsi_release_host(dc);
4099         return err;
4100 }
4101 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
4102
4103 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
4104 {
4105         u32 val;
4106         int ret = 0;
4107
4108         if (dsi->info.ulpm_not_supported)
4109                 return 0;
4110
4111         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
4112                 if (atomic_read(&dsi_syncpt_rst))
4113                         tegra_dsi_syncpt_reset(dsi);
4114
4115         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4116         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
4117         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
4118         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4119
4120         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
4121                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
4122                 if (ret < 0) {
4123                         dev_err(&dsi->dc->ndev->dev,
4124                                 "DSI syncpt for ulpm enter failed\n");
4125                         return ret;
4126                 }
4127         } else {
4128                 /* TODO: Find exact delay required */
4129                 mdelay(10);
4130         }
4131         dsi->ulpm = true;
4132
4133         return ret;
4134 }
4135
4136 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
4137 {
4138         u32 val;
4139         int ret = 0;
4140
4141         if (dsi->info.ulpm_not_supported)
4142                 return 0;
4143
4144         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
4145                 if (atomic_read(&dsi_syncpt_rst))
4146                         tegra_dsi_syncpt_reset(dsi);
4147
4148         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4149         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
4150         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
4151         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4152
4153         if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) {
4154                 ret = tegra_dsi_syncpt(dsi, TEGRA_DSI_LINK0);
4155                 if (ret < 0) {
4156                         dev_err(&dsi->dc->ndev->dev,
4157                                 "DSI syncpt for ulpm exit failed\n");
4158                         return ret;
4159                 }
4160         } else {
4161                 /* TODO: Find exact delay required */
4162                 mdelay(10);
4163         }
4164         dsi->ulpm = false;
4165
4166         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
4167         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
4168         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
4169         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
4170
4171         return ret;
4172 }
4173
4174 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
4175                                      struct tegra_dc_dsi_data *dsi,
4176                                      int no_of_frames)
4177 {
4178         int err;
4179         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
4180         u8 lp_op = dsi->status.lp_op;
4181         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
4182
4183         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
4184                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
4185                                 TEGRA_DSI_DRIVEN_BY_DC);
4186                 if (err < 0) {
4187                         dev_err(&dc->ndev->dev,
4188                                 "Switch to HS host mode failed\n");
4189                         return;
4190                 }
4191         }
4192
4193         /*
4194          * Some panels need DC frames be sent under certain
4195          * conditions. We are working on the right fix for this
4196          * requirement, while using this current fix.
4197          */
4198         tegra_dsi_start_dc_stream(dc, dsi);
4199
4200         /*
4201          * Send frames in Continuous or One-shot mode.
4202          */
4203         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4204                 /* FIX ME: tegra_dc_blank() implicitly takes lock */
4205                 int flag = mutex_is_locked(&dc->lock);
4206                 if (flag)
4207                         mutex_unlock(&dc->lock);
4208                 while (no_of_frames--)
4209                         tegra_dc_blank(dc, BLANK_ALL);
4210                 if (flag)
4211                         mutex_lock(&dc->lock);
4212         } else
4213                 mdelay(no_of_frames * frame_period);
4214
4215         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4216
4217         if (switch_to_lp) {
4218                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
4219                 if (err < 0)
4220                         dev_err(&dc->ndev->dev,
4221                                 "DSI failed to go to LP mode\n");
4222         }
4223 }
4224
4225 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
4226 {
4227         int err = 0;
4228
4229         if (dsi->avdd_dsi_csi)
4230                 err = regulator_enable(dsi->avdd_dsi_csi);
4231         WARN(err, "unable to enable regulator");
4232
4233         dsi->status.init = DSI_MODULE_INIT;
4234         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
4235         dsi->status.driven = DSI_DRIVEN_MODE_DC;
4236         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4237         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
4238         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
4239         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
4240
4241         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
4242                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
4243         else
4244                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
4245
4246         if (!(dsi->info.ganged_type)) {
4247                 if (dsi->info.video_burst_mode ==
4248                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
4249                         dsi->info.video_burst_mode ==
4250                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
4251                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
4252                 else
4253                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
4254         }
4255
4256         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
4257                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
4258         else
4259                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
4260
4261         tegra_dsi_clk_enable(dsi);
4262
4263         dsi->enabled = true;
4264 }
4265
4266 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4267 {
4268         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4269         int err = 0;
4270
4271         sysedp_set_state(dc->sysedpc, 1);
4272         mutex_lock(&dsi->lock);
4273         tegra_dc_io_start(dc);
4274
4275         /*
4276          * Do not program this panel as the bootloader as has already
4277          * initialized it. This avoids periods of blanking during boot.
4278          */
4279         if (dc->initialized) {
4280                 tegra_dsi_setup_initialized_panel(dsi);
4281                 goto fail;
4282         }
4283
4284         /* Stop DC stream before configuring DSI registers
4285          * to avoid visible glitches on panel during transition
4286          * from bootloader to kernel driver
4287          */
4288         tegra_dsi_stop_dc_stream(dc, dsi);
4289
4290         if (dsi->enabled) {
4291                 if (dsi->ulpm) {
4292                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4293                                 dev_err(&dc->ndev->dev,
4294                                         "DSI failed to exit ulpm\n");
4295                                 goto fail;
4296                         }
4297                 }
4298
4299                 if (dsi->info.panel_reset) {
4300                         /*
4301                          * Certain panels need dc frames be sent before
4302                          * waking panel.
4303                          */
4304                         if (dsi->info.panel_send_dc_frames)
4305                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4306
4307                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4308                                                         dsi->info.dsi_init_cmd,
4309                                                         dsi->info.n_init_cmd);
4310                         if (err < 0) {
4311                                 dev_err(&dc->ndev->dev,
4312                                 "dsi: error sending dsi init cmd\n");
4313                                 goto fail;
4314                         }
4315                 } else if (dsi->info.dsi_late_resume_cmd) {
4316                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4317                                                 dsi->info.dsi_late_resume_cmd,
4318                                                 dsi->info.n_late_resume_cmd);
4319                         if (err < 0) {
4320                                 dev_err(&dc->ndev->dev,
4321                                 "dsi: error sending late resume cmd\n");
4322                                 goto fail;
4323                         }
4324                 }
4325         } else {
4326                 err = tegra_dsi_init_hw(dc, dsi);
4327                 if (err < 0) {
4328                         dev_err(&dc->ndev->dev,
4329                                 "dsi: not able to init dsi hardware\n");
4330                         goto fail;
4331                 }
4332
4333                 if (dsi->ulpm) {
4334                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4335                                 dev_err(&dc->ndev->dev,
4336                                         "DSI failed to enter ulpm\n");
4337                                 goto fail;
4338                         }
4339
4340                         tegra_dsi_pad_enable(dsi);
4341
4342                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4343                                 dev_err(&dc->ndev->dev,
4344                                         "DSI failed to exit ulpm\n");
4345                                 goto fail;
4346                         }
4347                 }
4348
4349                 /*
4350                  * Certain panels need dc frames be sent before
4351                  * waking panel.
4352                  */
4353                 if (dsi->info.panel_send_dc_frames)
4354                         tegra_dsi_send_dc_frames(dc, dsi, 2);
4355
4356                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4357                 if (err < 0) {
4358                         dev_err(&dc->ndev->dev,
4359                                 "dsi: not able to set to lp mode\n");
4360                         goto fail;
4361                 }
4362
4363                 if (dsi->info.lp00_pre_panel_wakeup)
4364                         tegra_dsi_pad_disable(dsi);
4365
4366                 dsi->enabled = true;
4367         }
4368
4369         if (dsi->out_ops && dsi->out_ops->enable)
4370                 dsi->out_ops->enable(dsi);
4371 fail:
4372         tegra_dc_io_end(dc);
4373         mutex_unlock(&dsi->lock);
4374 }
4375
4376 static void tegra_dc_dsi_postpoweron(struct tegra_dc *dc)
4377 {
4378         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4379         int err = 0;
4380
4381         /*
4382          * Do not configure. Use bootloader configuration.
4383          * This avoids periods of blanking during boot.
4384          */
4385         if (dc->initialized)
4386                 return;
4387
4388         mutex_lock(&dsi->lock);
4389         tegra_dc_io_start(dc);
4390
4391         if (dsi->enabled) {
4392                 if (dsi->info.lp00_pre_panel_wakeup)
4393                         tegra_dsi_pad_enable(dsi);
4394
4395                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
4396                                                         dsi->info.n_init_cmd);
4397                 if (err < 0) {
4398                         dev_err(&dc->ndev->dev,
4399                                 "dsi: error while sending dsi init cmd\n");
4400                         goto fail;
4401                 }
4402
4403                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
4404                                 TEGRA_DSI_DRIVEN_BY_DC);
4405                 if (err < 0) {
4406                         dev_err(&dc->ndev->dev,
4407                                 "dsi: not able to set to hs mode\n");
4408                         goto fail;
4409                 }
4410
4411                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
4412                         tegra_dsi_start_dc_stream(dc, dsi);
4413
4414                 dsi->host_suspended = false;
4415         }
4416 fail:
4417         tegra_dc_io_end(dc);
4418         mutex_unlock(&dsi->lock);
4419 }
4420
4421 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
4422 {
4423         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4424
4425 #ifdef CONFIG_DEBUG_FS
4426         tegra_dc_dsi_debug_create(dsi);
4427 #endif
4428
4429         if (dsi->info.dsi2lvds_bridge_enable)
4430                 dsi->out_ops = &tegra_dsi2lvds_ops;
4431         else if (dsi->info.dsi2edp_bridge_enable)
4432                 dsi->out_ops = &tegra_dsi2edp_ops;
4433         else
4434                 dsi->out_ops = NULL;
4435
4436         if (dsi->out_ops && dsi->out_ops->init)
4437                 dsi->out_ops->init(dsi);
4438
4439         tegra_dsi_init_sw(dc, dsi);
4440 }
4441
4442 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
4443                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
4444 {
4445         u16 i;
4446         u16 len;
4447
4448         memcpy(dst, src, sizeof(*dst) * n_cmd);
4449
4450         for (i = 0; i < n_cmd; i++)
4451                 if (src[i].pdata) {
4452                         len = sizeof(*src[i].pdata) *
4453                                         src[i].sp_len_dly.data_len;
4454                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
4455                         if (!dst[i].pdata)
4456                                 goto free_cmd_pdata;
4457                         memcpy(dst[i].pdata, src[i].pdata, len);
4458                 }
4459
4460         return 0;
4461
4462 free_cmd_pdata:
4463         while (i--)
4464                 if (dst[i].pdata)
4465                         kfree(dst[i].pdata);
4466         return -ENOMEM;
4467 }
4468
4469 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
4470                                                 struct tegra_dsi_out *p_dsi)
4471 {
4472         struct tegra_dsi_cmd *p_init_cmd;
4473         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
4474         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
4475         struct tegra_dsi_cmd *p_suspend_cmd;
4476         int err = 0;
4477
4478         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
4479                 return -EINVAL;
4480
4481         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
4482                                 p_dsi->n_init_cmd, GFP_KERNEL);
4483         if (!p_init_cmd)
4484                 return -ENOMEM;
4485
4486         if (p_dsi->dsi_early_suspend_cmd) {
4487                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
4488                                         p_dsi->n_early_suspend_cmd,
4489                                         GFP_KERNEL);
4490                 if (!p_early_suspend_cmd) {
4491                         err = -ENOMEM;
4492                         goto err_free_init_cmd;
4493                 }
4494         }
4495
4496         if (p_dsi->dsi_late_resume_cmd) {
4497                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
4498                                         p_dsi->n_late_resume_cmd,
4499                                         GFP_KERNEL);
4500                 if (!p_late_resume_cmd) {
4501                         err = -ENOMEM;
4502                         goto err_free_p_early_suspend_cmd;
4503                 }
4504         }
4505
4506         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
4507                                 GFP_KERNEL);
4508         if (!p_suspend_cmd) {
4509                 err = -ENOMEM;
4510                 goto err_free_p_late_resume_cmd;
4511         }
4512
4513         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
4514
4515         /* Copy panel init cmd */
4516         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
4517                                                 p_init_cmd, p_dsi->n_init_cmd);
4518         if (err < 0)
4519                 goto err_free;
4520         dsi->info.dsi_init_cmd = p_init_cmd;
4521
4522         /* Copy panel early suspend cmd */
4523         if (p_dsi->dsi_early_suspend_cmd) {
4524                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
4525                                         p_early_suspend_cmd,
4526                                         p_dsi->n_early_suspend_cmd);
4527                 if (err < 0)
4528                         goto err_free;
4529                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
4530         }
4531
4532         /* Copy panel late resume cmd */
4533         if (p_dsi->dsi_late_resume_cmd) {
4534                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
4535                                                 p_late_resume_cmd,
4536                                                 p_dsi->n_late_resume_cmd);
4537                 if (err < 0)
4538                         goto err_free;
4539                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
4540         }
4541
4542         /* Copy panel suspend cmd */
4543         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
4544                                         p_dsi->n_suspend_cmd);
4545         if (err < 0)
4546                 goto err_free;
4547         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
4548
4549         if (!dsi->info.panel_reset_timeout_msec)
4550                 dsi->info.panel_reset_timeout_msec =
4551                                                 DEFAULT_PANEL_RESET_TIMEOUT;
4552         if (!dsi->info.panel_buffer_size_byte)
4553                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
4554
4555         if (!dsi->info.max_panel_freq_khz) {
4556                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
4557
4558                 if (dsi->info.video_burst_mode >
4559                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
4560                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
4561                                         "is not set for DSI burst mode.\n");
4562                         dsi->info.video_burst_mode =
4563                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
4564                 }
4565         }
4566
4567         if (!dsi->info.lp_cmd_mode_freq_khz)
4568                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
4569
4570         if (!dsi->info.lp_read_cmd_mode_freq_khz)
4571                 dsi->info.lp_read_cmd_mode_freq_khz =
4572                         dsi->info.lp_cmd_mode_freq_khz;
4573
4574         /* host mode is for testing only */
4575         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
4576         return 0;
4577
4578 err_free:
4579         kfree(p_suspend_cmd);
4580 err_free_p_late_resume_cmd:
4581         kfree(p_late_resume_cmd);
4582 err_free_p_early_suspend_cmd:
4583         kfree(p_early_suspend_cmd);
4584 err_free_init_cmd:
4585         kfree(p_init_cmd);
4586         return err;
4587 }
4588
4589 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
4590 {
4591         struct tegra_dc_dsi_data *dsi;
4592         struct resource *res;
4593         struct resource *base_res;
4594         struct resource dsi_res;
4595         void __iomem *base;
4596         struct clk *dc_clk = NULL;
4597         struct clk *dsi_clk;
4598         struct clk *dsi_fixed_clk = NULL;
4599         struct clk *dsi_lp_clk = NULL;
4600         struct tegra_dsi_out *dsi_pdata = NULL;
4601         int err = 0, i;
4602         int dsi_instance;
4603         char *ganged_reg_name[2] = {"ganged_dsia_regs", "ganged_dsib_regs"};
4604         char *dsi_clk_name[2] = {"dsia", "dsib"};
4605         char *dsi_lp_clk_name[2] = {"dsialp", "dsiblp"};
4606         struct device_node *np = dc->ndev->dev.of_node;
4607 #ifdef CONFIG_OF
4608         struct device_node *np_dsi =
4609                 of_find_node_by_path(DSI_NODE);
4610 #else
4611         struct device_node *np_dsi = NULL;
4612 #endif
4613         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4614         if (!dsi) {
4615                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
4616                 of_node_put(np_dsi);
4617                 return -ENOMEM;
4618         }
4619
4620         dsi->max_instances = dc->out->dsi->ganged_type ? MAX_DSI_INSTANCE : 1;
4621         dsi_instance = (int)dc->out->dsi->dsi_instance;
4622         for (i = 0; i < dsi->max_instances; i++) {
4623                 if (np) {
4624                         if (np_dsi && of_device_is_available(np_dsi)) {
4625                                 if (!dc->out->dsi->ganged_type)
4626                                         of_address_to_resource(np_dsi,
4627                                                 dsi_instance, &dsi_res);
4628                                 else /* ganged type */
4629                                         of_address_to_resource(np_dsi,
4630                                                 i, &dsi_res);
4631                                 res = &dsi_res;
4632                         } else {
4633                                 err = -EINVAL;
4634                                 goto err_free_dsi;
4635                         }
4636                 } else {
4637                         res = platform_get_resource_byname(dc->ndev,
4638                                         IORESOURCE_MEM,
4639                                         dc->out->dsi->ganged_type ?
4640                                         ganged_reg_name[i] : "dsi_regs");
4641                 }
4642                 if (!res) {
4643                         dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
4644                         err = -ENOENT;
4645                         goto err_free_dsi;
4646                 }
4647
4648                 base_res = request_mem_region(res->start, resource_size(res),
4649                                         dc->ndev->name);
4650                 if (!base_res) {
4651                         dev_err(&dc->ndev->dev,
4652                                 "dsi: request_mem_region failed\n");
4653                         err = -EBUSY;
4654                         goto err_free_dsi;
4655                 }
4656
4657                 base = ioremap(res->start, resource_size(res));
4658                 if (!base) {
4659                         dev_err(&dc->ndev->dev,
4660                                 "dsi: registers can't be mapped\n");
4661                         err = -EBUSY;
4662                         goto err_release_regs;
4663                 }
4664
4665                 dsi_pdata = dc->pdata->default_out->dsi;
4666                 if (!dsi_pdata) {
4667                         dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
4668                         goto err_release_regs;
4669                 }
4670
4671                 dsi_clk = dsi_pdata->dsi_instance ?
4672                                 clk_get(&dc->ndev->dev,
4673                                 dsi_clk_name[DSI_INSTANCE_1]) :
4674                                 clk_get(&dc->ndev->dev, dsi_clk_name[i]);
4675                 dsi_lp_clk = dsi_pdata->dsi_instance ?
4676                                 clk_get(&dc->ndev->dev,
4677                                 dsi_lp_clk_name[DSI_INSTANCE_1]) :
4678                                 clk_get(&dc->ndev->dev, dsi_lp_clk_name[i]);
4679
4680                 if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_lp_clk)) {
4681                         dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
4682                         err = -EBUSY;
4683                         goto err_dsi_clk_put;
4684                 }
4685
4686                 dsi->base[i] = base;
4687                 dsi->base_res[i] = base_res;
4688                 dsi->dsi_clk[i] = dsi_clk;
4689                 dsi->dsi_lp_clk[i] = dsi_lp_clk;
4690         }
4691
4692         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
4693
4694         if (IS_ERR_OR_NULL(dsi_fixed_clk)) {
4695                 dev_err(&dc->ndev->dev, "dsi: can't get fixed clock\n");
4696                 err = -EBUSY;
4697                 goto err_release_regs;
4698         }
4699
4700         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
4701         if (IS_ERR_OR_NULL(dc_clk)) {
4702                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
4703                         dev_name(&dc->ndev->dev));
4704                 err = -EBUSY;
4705                 goto err_dsi_fixed_clk_put;
4706         }
4707
4708         mutex_init(&dsi->lock);
4709         dsi->dc = dc;
4710         dsi->dc_clk = dc_clk;
4711         dsi->dsi_fixed_clk = dsi_fixed_clk;
4712
4713         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
4714         if (err < 0)
4715                 goto err_dc_clk_put;
4716
4717         tegra_dc_set_outdata(dc, dsi);
4718         __tegra_dc_dsi_init(dc);
4719
4720         /*
4721          * Enable DPD mode for DSI pads if required.
4722          */
4723         if (!dsi->info.ganged_type &&
4724                 (dsi->info.controller_vs >= DSI_VS_1)) {
4725                 if (dsi->info.dpd_dsi_pads & DSI_DPD_EN)
4726                         tegra_io_dpd_enable(&dsi_io);
4727                 if (dsi->info.dpd_dsi_pads & DSIB_DPD_EN)
4728                         tegra_io_dpd_enable(&dsib_io);
4729                 if (dsi->info.dpd_dsi_pads & DSIC_DPD_EN)
4730                         tegra_io_dpd_enable(&dsic_io);
4731                 if (dsi->info.dpd_dsi_pads & DSID_DPD_EN)
4732                         tegra_io_dpd_enable(&dsid_io);
4733         }
4734
4735         of_node_put(np_dsi);
4736         return 0;
4737
4738 err_dc_clk_put:
4739         clk_put(dc_clk);
4740 err_dsi_fixed_clk_put:
4741         clk_put(dsi_fixed_clk);
4742 err_dsi_clk_put:
4743         for (i = 0; i < dsi->max_instances; i++) {
4744                 clk_put(dsi->dsi_lp_clk[i]);
4745                 clk_put(dsi->dsi_clk[i]);
4746         }
4747 err_release_regs:
4748         for (i = 0; i < dsi->max_instances; i++)
4749                 release_resource(dsi->base_res[i]);
4750 err_free_dsi:
4751         kfree(dsi);
4752
4753         of_node_put(np_dsi);
4754         return err;
4755 }
4756
4757 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
4758 {
4759         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4760         u16 i;
4761         u32 val;
4762
4763         mutex_lock(&dsi->lock);
4764         tegra_dc_io_start(dc);
4765
4766         if (dsi->out_ops && dsi->out_ops->destroy)
4767                 dsi->out_ops->destroy(dsi);
4768
4769         /* free up the pdata */
4770         for (i = 0; i < dsi->info.n_init_cmd; i++) {
4771                 if (dsi->info.dsi_init_cmd[i].pdata)
4772                         kfree(dsi->info.dsi_init_cmd[i].pdata);
4773         }
4774         kfree(dsi->info.dsi_init_cmd);
4775
4776         /* Disable dc stream */
4777         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4778                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4779
4780         /* Disable dsi phy clock */
4781         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
4782                 tegra_dsi_hs_clk_out_disable(dc, dsi);
4783
4784         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4785         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4786
4787         for (i = 0; i < dsi->max_instances; i++) {
4788                 iounmap(dsi->base[i]);
4789                 release_resource(dsi->base_res[i]);
4790         }
4791         clk_put(dsi->dc_clk);
4792         for (i = 0; i < dsi->max_instances; i++)
4793                 clk_put(dsi->dsi_clk[i]);
4794
4795         tegra_dc_io_end(dc);
4796         mutex_unlock(&dsi->lock);
4797         mutex_destroy(&dsi->lock);
4798         kfree(dsi);
4799 }
4800
4801 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4802                                                         u32 settings)
4803 {
4804         struct clk *parent_clk = NULL;
4805         struct clk *base_clk = NULL;
4806         int i = 0;
4807
4808         for (i = 0; i < dsi->max_instances; i++) {
4809                 parent_clk = clk_get_parent(dsi->dsi_clk[i]);
4810                 base_clk = clk_get_parent(parent_clk);
4811
4812 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
4813                 if (dsi->info.dsi_instance)
4814                         tegra_clk_cfg_ex(base_clk,
4815                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
4816                                         settings);
4817                 else
4818                         tegra_clk_cfg_ex(base_clk,
4819                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
4820                                         settings);
4821 #else
4822                 tegra_clk_cfg_ex(base_clk,
4823                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
4824                                 settings);
4825 #endif
4826         }
4827 }
4828
4829 static int tegra_dsi_te_on_off(struct tegra_dc_dsi_data *dsi, bool flag)
4830 {
4831         int ret;
4832
4833         struct tegra_dsi_cmd te_enable[] = {
4834                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4835                                 DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
4836                 DSI_DLY_MS(0),
4837         };
4838
4839         struct tegra_dsi_cmd te_disable[] = {
4840                 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4841                                 DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0),
4842                 DSI_DLY_MS(0),
4843         };
4844
4845         if (flag)
4846                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_enable,
4847                                         ARRAY_SIZE(te_enable));
4848         else
4849                 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_disable,
4850                                         ARRAY_SIZE(te_disable));
4851
4852         return ret;
4853 }
4854
4855 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4856                                         struct tegra_dc_dsi_data *dsi,
4857                                         u32 suspend_aggr)
4858 {
4859         u32 val = 0;
4860         int err = 0;
4861
4862         switch (suspend_aggr) {
4863         case DSI_HOST_SUSPEND_LV2:
4864                 if (!dsi->ulpm) {
4865                         err = tegra_dsi_enter_ulpm(dsi);
4866                         if (err < 0) {
4867                                 dev_err(&dc->ndev->dev,
4868                                         "DSI failed to enter ulpm\n");
4869                                 goto fail;
4870                         }
4871                 }
4872
4873                 tegra_dsi_pad_disable(dsi);
4874
4875                 /* Suspend core-logic */
4876                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4877                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4878
4879                 /* disable HS logic */
4880                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4881                 val |= DSI_PAD_PDVCLAMP(0x1);
4882                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4883
4884                 /* fall through */
4885         case DSI_HOST_SUSPEND_LV1:
4886                 /* Disable dsi fast and slow clock */
4887                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4888                 /* fall through */
4889         case DSI_HOST_SUSPEND_LV0:
4890                 /* Disable dsi source clock */
4891                 tegra_dsi_clk_disable(dsi);
4892                 break;
4893         case DSI_NO_SUSPEND:
4894                 break;
4895         default:
4896                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
4897                                                 "is not supported.\n");
4898         }
4899
4900         tegra_dvfs_set_rate(dc->clk, 0);
4901
4902         return 0;
4903 fail:
4904         return err;
4905 }
4906
4907 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
4908                                         struct tegra_dc_dsi_data *dsi,
4909                                         u32 suspend_aggr)
4910 {
4911         u32 val;
4912         int err;
4913
4914         switch (dsi->info.suspend_aggr) {
4915         case DSI_HOST_SUSPEND_LV0:
4916                 tegra_dsi_clk_enable(dsi);
4917                 break;
4918         case DSI_HOST_SUSPEND_LV1:
4919                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4920                 tegra_dsi_clk_enable(dsi);
4921                 break;
4922         case DSI_HOST_SUSPEND_LV2:
4923                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4924                 tegra_dsi_clk_enable(dsi);
4925
4926                 /* enable HS logic */
4927                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
4928                 val &= ~DSI_PAD_PDVCLAMP(0x1);
4929                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
4930
4931                 tegra_dsi_writel(dsi,
4932                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
4933                         DSI_POWER_CONTROL);
4934
4935                 if (dsi->ulpm) {
4936                         err = tegra_dsi_enter_ulpm(dsi);
4937                         if (err < 0) {
4938                                 dev_err(&dc->ndev->dev,
4939                                         "DSI failed to enter ulpm\n");
4940                                 goto fail;
4941                         }
4942
4943                         tegra_dsi_pad_enable(dsi);
4944
4945                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4946                                 dev_err(&dc->ndev->dev,
4947                                         "DSI failed to exit ulpm\n");
4948                                 goto fail;
4949                         }
4950                 } else {
4951                         tegra_dsi_pad_enable(dsi);
4952                 }
4953                 break;
4954         case DSI_NO_SUSPEND:
4955                 break;
4956         default:
4957                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
4958                                                 "is not supported.\n");
4959         }
4960
4961         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4962
4963         return 0;
4964 fail:
4965         return err;
4966 }
4967
4968 static int tegra_dsi_host_suspend_trylock(struct tegra_dc *dc,
4969                                         struct tegra_dc_dsi_data *dsi)
4970 {
4971         if (!mutex_trylock(&dc->one_shot_lock))
4972                 goto fail;
4973         if (!mutex_trylock(&dc->lp_lock))
4974                 goto unlock_one_shot_lock;
4975         if (!mutex_trylock(&dc->lock))
4976                 goto unlock_lp_lock;
4977         if (!mutex_trylock(&dsi->host_lock))
4978                 goto unlock_dc_lock;
4979
4980         return 1;
4981
4982 unlock_dc_lock:
4983         mutex_unlock(&dc->lock);
4984 unlock_lp_lock:
4985         mutex_unlock(&dc->lp_lock);
4986 unlock_one_shot_lock:
4987         mutex_unlock(&dc->one_shot_lock);
4988 fail:
4989         return 0;
4990 }
4991
4992 static void tegra_dsi_host_suspend_unlock(struct tegra_dc *dc,
4993                                         struct tegra_dc_dsi_data *dsi)
4994 {
4995         mutex_unlock(&dsi->host_lock);
4996         mutex_unlock(&dc->lock);
4997         mutex_unlock(&dc->lp_lock);
4998         mutex_unlock(&dc->one_shot_lock);
4999 }
5000
5001 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
5002 {
5003         int err = 0;
5004         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5005
5006         if (!dsi->enabled)
5007                 return -EINVAL;
5008
5009         while (!tegra_dsi_host_suspend_trylock(dc, dsi))
5010                 cond_resched();
5011
5012         if (dsi->host_suspended || atomic_read(&dsi->host_ref)) {
5013                 tegra_dsi_host_suspend_unlock(dc, dsi);
5014                 return 0;
5015         }
5016
5017         tegra_dc_io_start(dc);
5018
5019         dsi->host_suspended = true;
5020
5021         tegra_dsi_stop_dc_stream(dc, dsi);
5022
5023         tegra_dsi_te_on_off(dsi, false);
5024
5025         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
5026         if (err < 0) {
5027                 dev_err(&dc->ndev->dev,
5028                         "DSI host suspend failed\n");
5029                 goto fail;
5030         }
5031
5032         /* Shutting down. Drop any reference to dc clk */
5033         while (tegra_is_clk_enabled(dc->clk))
5034                 tegra_dc_put(dc);
5035
5036         pm_runtime_put_sync(&dc->ndev->dev);
5037 fail:
5038         tegra_dc_io_end(dc);
5039         tegra_dsi_host_suspend_unlock(dc, dsi);
5040         return err;
5041 }
5042
5043 static bool tegra_dc_dsi_osidle(struct tegra_dc *dc)
5044 {
5045         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5046
5047         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5048                 return dsi->host_suspended;
5049         else
5050                 return false;
5051 }
5052
5053 static void tegra_dsi_bl_off(struct backlight_device *bd)
5054 {
5055         if (!bd)
5056                 return;
5057
5058         bd->props.brightness = 0;
5059         backlight_update_status(bd);
5060 }
5061
5062 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
5063                                 struct tegra_dc_dsi_data *dsi)
5064 {
5065         int val = 0;
5066         int err = 0;
5067
5068         if (!dsi->enabled)
5069                 return 0;
5070
5071         cancel_delayed_work(&dsi->idle_work);
5072
5073         tegra_dsi_bl_off(get_backlight_device_by_name(dsi->info.bl_name));
5074
5075         /* Suspend DSI panel */
5076         err = tegra_dsi_send_panel_cmd(dc, dsi,
5077                         dsi->info.dsi_suspend_cmd,
5078                         dsi->info.n_suspend_cmd);
5079
5080         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
5081         if (err < 0) {
5082                 dev_err(&dc->ndev->dev,
5083                 "DSI failed to go to LP mode\n");
5084                 goto fail;
5085         }
5086
5087         /*
5088          * Certain panels need dc frames be sent after
5089          * putting panel to sleep.
5090          */
5091         if (dsi->info.panel_send_dc_frames)
5092                 tegra_dsi_send_dc_frames(dc, dsi, 2);
5093
5094         if (!dsi->ulpm) {
5095                 err = tegra_dsi_enter_ulpm(dsi);
5096                 if (err < 0) {
5097                         dev_err(&dc->ndev->dev,
5098                                 "DSI failed to enter ulpm\n");
5099                         goto fail;
5100                 }
5101         }
5102
5103         tegra_dsi_pad_disable(dsi);
5104
5105         /* Suspend core-logic */
5106         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
5107         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
5108
5109         /* Disable dsi fast and slow clock */
5110         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
5111
5112         /* Disable dsi source clock */
5113         tegra_dsi_clk_disable(dsi);
5114
5115         dsi->enabled = false;
5116         dsi->host_suspended = true;
5117
5118         return 0;
5119 fail:
5120         return err;
5121 }
5122
5123 static void tegra_dc_dsi_postpoweroff(struct tegra_dc *dc)
5124 {
5125         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5126
5127         /* Do not disable regulator when device is shutting down */
5128         if (!dsi->device_shutdown && !dsi->enabled && dsi->avdd_dsi_csi)
5129                 regulator_disable(dsi->avdd_dsi_csi);
5130 }
5131 static void tegra_dc_dsi_shutdown(struct tegra_dc *dc)
5132 {
5133         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5134
5135         dsi->device_shutdown = true;
5136 }
5137 static int tegra_dsi_host_resume(struct tegra_dc *dc)
5138 {
5139         int err = 0;
5140         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5141
5142         if (!dsi->enabled)
5143                 return -EINVAL;
5144
5145         cancel_delayed_work(&dsi->idle_work);
5146
5147         mutex_lock(&dsi->host_lock);
5148         if (!dsi->host_suspended) {
5149                 mutex_unlock(&dsi->host_lock);
5150                 return 0;
5151         }
5152
5153         tegra_dc_io_start(dc);
5154
5155         pm_runtime_get_sync(&dc->ndev->dev);
5156
5157         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
5158         if (err < 0) {
5159                 dev_err(&dc->ndev->dev,
5160                         "DSI host resume failed\n");
5161                 goto fail;
5162         }
5163
5164         tegra_dsi_te_on_off(dsi, true);
5165
5166         tegra_dsi_start_dc_stream(dc, dsi);
5167         dsi->host_suspended = false;
5168 fail:
5169         tegra_dc_io_end(dc);
5170         mutex_unlock(&dsi->host_lock);
5171         return err;
5172 }
5173
5174 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
5175 {
5176         int err;
5177         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5178
5179         if (dsi->host_suspended)
5180                 tegra_dsi_host_resume(dc);
5181
5182         sysedp_set_state(dc->sysedpc, 0);
5183         mutex_lock(&dsi->lock);
5184         tegra_dc_io_start(dc);
5185
5186         if (!dsi->info.suspend_stop_stream_late)
5187                 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
5188                         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
5189
5190         if (dsi->out_ops && dsi->out_ops->disable)
5191                 dsi->out_ops->disable(dsi);
5192
5193         if (dsi->info.power_saving_suspend) {
5194                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
5195                         dev_err(&dc->ndev->dev,
5196                                 "DSI failed to enter deep sleep\n");
5197                         goto fail;
5198                 }
5199         } else {
5200                 if (dsi->info.dsi_early_suspend_cmd) {
5201                         err = tegra_dsi_send_panel_cmd(dc, dsi,
5202                                 dsi->info.dsi_early_suspend_cmd,
5203                                 dsi->info.n_early_suspend_cmd);
5204                         if (err < 0) {
5205                                 dev_err(&dc->ndev->dev,
5206                                 "dsi: Error sending early suspend cmd\n");
5207                                 goto fail;
5208                         }
5209                 }
5210
5211                 if (!dsi->ulpm) {
5212                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
5213                                 dev_err(&dc->ndev->dev,
5214                                         "DSI failed to enter ulpm\n");
5215                                 goto fail;
5216                         }
5217                 }
5218         }
5219
5220         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
5221                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
5222
5223 fail:
5224         mutex_unlock(&dsi->lock);
5225         tegra_dc_io_end(dc);
5226 }
5227
5228 #ifdef CONFIG_PM
5229 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
5230 {
5231         struct tegra_dc_dsi_data *dsi;
5232
5233         dsi = tegra_dc_get_outdata(dc);
5234
5235         if (!dsi->enabled)
5236                 return;
5237
5238         if (dsi->host_suspended)
5239                 tegra_dsi_host_resume(dc);
5240
5241         tegra_dc_io_start(dc);
5242         mutex_lock(&dsi->lock);
5243
5244         if (dsi->out_ops && dsi->out_ops->suspend)
5245                 dsi->out_ops->suspend(dsi);
5246
5247         if (!dsi->info.power_saving_suspend) {
5248                 if (dsi->ulpm) {
5249                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
5250                                 dev_err(&dc->ndev->dev,
5251                                         "DSI failed to exit ulpm");
5252                                 goto fail;
5253                         }
5254                 }
5255
5256                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
5257                         dev_err(&dc->ndev->dev,
5258                                 "DSI failed to enter deep sleep\n");
5259                         goto fail;
5260                 }
5261         }
5262 fail:
5263         mutex_unlock(&dsi->lock);
5264         tegra_dc_io_end(dc);
5265 }
5266
5267 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
5268 {
5269         struct tegra_dc_dsi_data *dsi;
5270
5271         dsi = tegra_dc_get_outdata(dc);
5272
5273         /* No dsi config required since tegra_dc_dsi_enable
5274          * will reconfigure the controller from scratch
5275          */
5276
5277          if (dsi->out_ops && dsi->out_ops->resume)
5278                 dsi->out_ops->resume(dsi);
5279 }
5280 #endif
5281
5282 static int tegra_dc_dsi_init(struct tegra_dc *dc)
5283 {
5284         struct tegra_dc_dsi_data *dsi;
5285         int err = 0;
5286
5287         err = _tegra_dc_dsi_init(dc);
5288         if (err < 0) {
5289                 dev_err(&dc->ndev->dev,
5290                         "dsi: Instance A init failed\n");
5291                 goto err;
5292         }
5293
5294         dsi = tegra_dc_get_outdata(dc);
5295
5296         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
5297         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
5298                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
5299                 err = -ENODEV;
5300                 goto err_reg;
5301         }
5302
5303         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
5304         if (IS_ERR(dsi->mipi_cal)) {
5305                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
5306                 err = PTR_ERR(dsi->mipi_cal);
5307                 goto err_mipi;
5308         }
5309         return 0;
5310 err_mipi:
5311         if (dsi->avdd_dsi_csi)
5312                 regulator_put(dsi->avdd_dsi_csi);
5313 err_reg:
5314         _tegra_dc_dsi_destroy(dc);
5315         tegra_dc_set_outdata(dc, NULL);
5316 err:
5317         return err;
5318 }
5319
5320 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
5321 {
5322         struct regulator *avdd_dsi_csi;
5323         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5324
5325         avdd_dsi_csi = dsi->avdd_dsi_csi;
5326
5327         _tegra_dc_dsi_destroy(dc);
5328         regulator_put(avdd_dsi_csi);
5329         tegra_mipi_cal_destroy(dc);
5330 }
5331
5332 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
5333 {
5334         unsigned long rate;
5335         struct clk *parent_clk;
5336         struct clk *base_clk;
5337         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5338
5339
5340         /* divide by 1000 to avoid overflow */
5341         dc->mode.pclk /= 1000;
5342         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
5343                                 / dc->shift_clk_div.div;
5344         rate *= 1000;
5345         dc->mode.pclk *= 1000;
5346
5347         if (dc->initialized)
5348                 goto skip_setup;
5349
5350         if (clk == dc->clk) {
5351                 parent_clk = clk_get_sys(NULL,
5352                                 dc->out->parent_clk ? : "pll_d_out0");
5353                 base_clk = clk_get_parent(parent_clk);
5354         } else {
5355                 if (dc->pdata->default_out->dsi->dsi_instance) {
5356                         parent_clk = clk_get_sys(NULL,
5357                                 dc->out->parent_clk ? : "pll_d2");
5358                         base_clk = clk_get_parent(parent_clk);
5359                 } else {
5360                         parent_clk = clk_get_sys(NULL,
5361                                 dc->out->parent_clk ? : "pll_d_out0");
5362                         base_clk = clk_get_parent(parent_clk);
5363                 }
5364         }
5365         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
5366
5367         if (rate != clk_get_rate(base_clk))
5368                 clk_set_rate(base_clk, rate);
5369
5370         if (clk_get_parent(clk) != parent_clk)
5371                 clk_set_parent(clk, parent_clk);
5372
5373 skip_setup:
5374         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
5375
5376         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
5377 }
5378
5379 static void tegra_dc_dsi_vrr_enable(struct tegra_dc *dc, bool enable)
5380 {
5381         struct tegra_vrr *vrr  = dc->out->vrr;
5382
5383         if (vrr)
5384                 vrr->enable = enable;
5385 }
5386
5387 static void tegra_dc_dsi_modeset_notifier(struct tegra_dc *dc)
5388 {
5389         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
5390
5391         if (dsi->info.ganged_type)
5392                 tegra_dsi_pix_correction(dc, dsi);
5393 }
5394
5395 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
5396         .init = tegra_dc_dsi_init,
5397         .destroy = tegra_dc_dsi_destroy,
5398         .enable = tegra_dc_dsi_enable,
5399         .postpoweron = tegra_dc_dsi_postpoweron,
5400         .disable = tegra_dc_dsi_disable,
5401         .postpoweroff = tegra_dc_dsi_postpoweroff,
5402         .hold = tegra_dc_dsi_hold_host,
5403         .release = tegra_dc_dsi_release_host,
5404         .shutdown = tegra_dc_dsi_shutdown,
5405 #ifdef CONFIG_PM
5406         .suspend = tegra_dc_dsi_suspend,
5407         .resume = tegra_dc_dsi_resume,
5408 #endif
5409         .setup_clk = tegra_dc_dsi_setup_clk,
5410         .osidle = tegra_dc_dsi_osidle,
5411         .vrr_enable = tegra_dc_dsi_vrr_enable,
5412         .modeset_notifier = tegra_dc_dsi_modeset_notifier,
5413 };