arm: tegra: Modify TEGRA_USE_DFLL_RANGE

Change TEGRA_USE_DFLL_RANGE to add one more range value
  "3" - DFLL usage is controlled by thermal cooling device

Bug 200002255

Change-Id: Ib8443e0f9574632e0e2370618175fd40132a4488
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/439760
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1ef9951708b5b87a727c0a26ae4bb8d632b92221..eed1a25d8d745f559490980672752a18d16e45a5 100644 (file)
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -693,7 +693,7 @@ config TEGRA_IO_DPD
 config TEGRA_USE_DFLL_RANGE
        int "Default CPU DFLL operating range"
        depends on ARCH_TEGRA_HAS_CL_DVFS
-       range 0 2
+       range 0 3
        default "0" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_21x_SOC
        default "1" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_13x_SOC
        default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
@@ -705,6 +705,7 @@ config TEGRA_USE_DFLL_RANGE
          "1" - DFLL is used as a source for all CPU rates
          "2" - DFLL is used only for high rates above crossover with
                PLL dvfs curve
+         "3" - DFLL usage is controlled by thermal cooling device
 
 config REGULATOR_TEGRA_DFLL_BYPASS
        bool "Use dfll bypass regulator"