arm: tegra: Modify TEGRA_USE_DFLL_RANGE

Change TEGRA_USE_DFLL_RANGE to add one more range value
  "3" - DFLL usage is controlled by thermal cooling device

Bug 200002255

Change-Id: Ib8443e0f9574632e0e2370618175fd40132a4488
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/439760
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

gpu: nvgpu: return error from mutex_acquire() if pmu not initialized

In pmu_mutex_acquire(), we return zero (success) if
pmu->initialized is not set

Since mutex_acquire() was successful, we then call
pmu_mutex_release()

If now pmu->initialized is set in some other thread
then we proceed to validate the mutex owner and
end up causing below warning :

pmu_mutex_release: requester 0x00000000 NOT match owner 0x00000008

Hence to fix this return error from mutex_acquire()
and mutex_release() if pmu->initialized is not yet set
and in that case we proceed to call elpg enable/disable

Bug 1533644

Change-Id: Ifbb9e6a8e13f6478a13e3f9d98ced11792cc881f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/439333
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar S <nkumars@nvidia.com>
Tested-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

video: tegra: dc: fix build break

Fix build break of uninitialized variables.

Bug 1536245
Bug 1371533

Change-Id: Ic16eef09566c82fc8cae7d949b9d8f687585766d
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/440604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm64: tegra: pinmux : enable e_input of sdmmc clk

For all SDMMC controllers, E_INPUT of CLK pad should be
enabled since loopback CLK (Zi of CLK pad) is used to
latch RESP/DATA coming from external device.
If not enabled, you will see RESP/DATA time outs.

Change-Id: Ia6c8ff1681f7f4dbcb5d9916f1593da5423f6999
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/440394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arm: tegra: ardbeg: remove avdd_3v3_dp rail

remove avdd_3v3_dp rail from the board
since device tree will handle this.

Bug 1371533

Change-Id: Iebe3a51580d53b1e2fd005eb7045cc609dee684b
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/439088
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: dts: arbdeg: add avdd_3v3_dp regulator

Add avdd_3v3_dp regulator in arbdeg which
use following panels.

 - panel-a-edp-1080p-14-0
 - panel-i-edp-1080p-11-6

Bug 1371533

Change-Id: I7baf7a0298d51a0b1337b26b8bf4cd0627e9338d
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/439083
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: dts: panel regulators' phandle in DT

Use panel regulators' phandle in device tree.

Bug 1371533

Change-Id: I19cfe17228261c32e13f89585343174e2e5565a3
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/438568
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

mfd: max77620: add details for battery backup charging parameters

Add sub node for backup battery charging and details their properties.

Change-Id: I7fd31377d1c60ea7b25ef085eafd86442d7d3fc3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/440377

mfd: max77620: add backup battery charging configuration

Add backup battery charging configuration for MAX77620.

Change-Id: I5f0f02f64906efaaac5dbf14f7f1bc9b539e1b69
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/440376

ARM: tegra: do not register console port from board file if it is from DT

If console port is registerd from DT then do not register it from
board files.

Add checks for node whether it is enable from DT or not and if not
then only register from board files.

Change-Id: I66c50e21c2520cc0046b7a919a4de0d6cea7c33f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/440365

ARM: tegra: add API to check whether console port is from DT or not

Add API to findout whether console port is from DT or not. This will
help to avoid the registration of console port from board files if
it is done from DT.

Change-Id: I7bcea63a1d902de188e0b0b94c26a62c01d65277
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/440364

video: tegra: dsi: turn off pads after calibration

Turn off mipi bias pads after calibration

Bug 200021693

Change-Id: Ia62e2e386fc766b15e1abaee1bacb873a326d1bf
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/438645
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: T132: update SoC therm caps, vmax trips table

update SoC therm caps table and vmax trips table

bug 1442659

Change-Id: I26cc83fd9f6fe2a2f806eed254e2d70ce00ff254
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/427836
(cherry picked from commit b43244429a736da523184a54f4ae930bbe622252)
Reviewed-on: http://git-master/r/432801
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

arm: tegra: update vco_min value for pll_x

udpate vco_min value for pll_x from 700MHz to
1.2GHz

bug 1526834

Change-Id: I5deb14b55e395a3ec964d59ce5dde4d8fabea79b
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/427853
(cherry picked from commit 3bf9e2a40c5ee8c42dbc2cbff616c65e4fea7eb4)
Reviewed-on: http://git-master/r/432800
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

arm64: dts: e2141: add derated tables for e2141

The emc derated tables are the same as used in bowmore

Bug 200021697

Change-Id: I4a8bc8ab985bda80d8c23c80fe94b087f2ba34b2
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/440010
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

gpu: nvgpu: Remove unused GK20A cooling device

Removed unused, obsolete GK20A cooling device.

Bug 1450787

Change-Id: I5b02546d0405dd518ec841d903e650a8d38db8f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437942
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Update clk sources for some xusb src clocks

Update clk sources for xusb_host_src, xusb_falcon_src, xusb_dev_src
Also update max freq for pll_re_vco and pll_re_out to 624MHz
based on clock policies

Change-Id: Ia627d6087d3cce388d2e85040b7bbb6514a395e5
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/439495
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21; Update mux for hda2codec_2x clock

Bug 1413190

Change-Id: I689861ad56b27e883bd0264dc29c1c24aaf339b6
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/439509
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Add xusb_padctl clock

Bug 1413190

Change-Id: I5c51746bba276bf999756c1f95fc798fe6b4523b
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/438979
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

video: tegra: Fix framebuffer modelist database

Framebuffer modelist database get corrupted on
adding more modes check with fake panel and
switching back to real panel. Fixed by removing
all the fake panel modes from framebuffer
database.

bug 1408446

Change-Id: I2f3c40515daa86f2010a2f236b517d59caddd4d2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/437402
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

arm: tegra: Support framebuffer list for fake panel

Add a function to handle the framebuffer list properly
between fake and real panel switching.

bug 1408446

Change-Id: Ibcadab792ede1f6cadca960b6a045747c07954c0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/437401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

video: tegra: dc: Fix pixelclock update issue

Fix the issue with Pixelclock not being updated on mode
changes for fake dsi panel.

bug 1408446

Change-Id: I0ebdd198666b00ced32d78e6961c3d9e8fec42cc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/435923
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

video: dc: Clarify TEGRA_DC_EXTENSIONS

bug 1535433

Change-Id: I73b0bfdc1e4dd07ef8b8f7ee809ac2e6bd723e6d
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/439652
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

arm: tegra: Add DT support for wakeup monitor

Add DT support for tegra wakeup monitor driver.

Bug 200013565

Change-Id: Ib3c40ce811fcd2d08210ba6880b1b095306b9d45
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/432777
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chun Xu <chunx@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

arm64: tegra: misc fixes to hardwood driver

* Set NS bit when kernel is non-secure
* fix potential race in late_init
* enable hotplug notifier in late_init
* set buf occupied if immediately available
* better debugging print

Change-Id: I7acd736888f05facc559c7c965e20aea6f43060c
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/439369
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

arm64: tegra: hotplug support for Denver hardwoord

Change-Id: Ifb524fe0a7061371136c380218fca8bc762b38ea
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/407169
Reviewed-on: http://git-master/r/416713
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

Revert "arm64: Get the number of bits in ASID from the CPU"

This reverts commit eebb6dcd0afb9dfa58c28b3e7b0a03747760b174.

Bug 1486987

Change-Id: Ibea6479529a04c02b69b682977c5f62e051a1fec
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/437334
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

video: tegra: dc: add color formats for t186

This patch adds new color formats introduced in parker to dc.h
and its helper functions in dc_priv.h

Change-Id: I9c15b7246fa7577159042636479692e2745a20bc
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/438905
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

ASoC: Tegra: Fix concurrent pcm and compress playback

- Added path between BE and codec stream
- use atomic reference count

Bug 1495249

Change-Id: I895d22e1854c53f41362ed2a1cff63d88feb397b
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/405859
(cherry picked from commit 6a3202ea03cba8b987a77ed4ec0010121c01dc03)
Reviewed-on: http://git-master/r/423692
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

arm64: tegra: fix pinmux dtsi for t210-ers-e2220

Delete some pinmux configs that are not required
from e2220 pinmux dtsi file. The same were already
removed from e2190 default generated file. Missed
these in e2220.

Change-Id: Ia973935ebd261afcf416dc0d5579689a8ac91962
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/440374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

video: tegra: hdmi: hpd framework

Bug 200006291

Change-Id: I4d3887670db090346129869f81f6b640d9912d09
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/439877
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ASoC: ad193x: Added DT support

This change is for adding device of_match table in ad193x driver
to support DT.

Bug 1442940

Change-Id: Ib4237822cd90be67710f04f72d86f7298c80482e
Signed-off-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-on: http://git-master/r/346393
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Tested-by: Justin Kim (SW-TEGRA) <juskim@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

arm: tegra: vcm30t124: Add GPU DVFS

Added separate function set_atomtv_gpu_dvfs_data for
construction of Automotive specific GPU DVFS Table as per
below formula.

GPU voltage (mV) = c0 + c1*speedo + c2*speedo*speedo if T > 34C
GPU voltage (mV) = c3 if T < 34C.

Vcm30t124 SOC Therm platform data clean up.

Bug 200006306

Change-Id: I55e82acfeb9a59b5c6754401b02b92c815d31005
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/411478
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

ARM64: mach: tegra: cleanup pdata for udc, otg

As DT support for udc and otg is enabled,
Cleanup pdata for udc and otg in board-t210ref.

Bug 200008312

Change-Id: I4c344b8d640226a0e9274e31a4926b8d3756e31b
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/438623
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Revert "arm64: tegra: T210: Add DSI support"

This reverts commit 5a4c3c63aebf1066eb3d9b363c8d736dbd50851b.
The "http://git-master/r/428959" w.r.t
"5a4c3c63aebf1066eb3d9b363c8d736dbd50851b" causes kernel
panic on t210 platform. Reverting this, kernel boots
fine.

Bug 1476583

Change-Id: Ibd17b801b2cb632d129d426f31caa844dc72dc57
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/440321
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

arm64: config: t210: enable MC clock domain

Change-Id: I759a08f3a9ca68598e645f063ba4ed099166a64f
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/436724
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

arm64: config: tegra21: enable VI one device

Enables VI one device, with this VI will have only one
device node under nvhost. This is needed for more than two camera
support.

Bug 1436477

Change-Id: I71e4ea4fbd4453cb8ef532ca98e0448dc5b26ab7
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/417125
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>

arm64: tegra: add pinmux/gpio dtsi for T210 ERS

Add T210-ERS dtsi files for GPIO/Pinmux

Bug 200021821

Change-Id: Idce0f0a689de113c51117cbdcc79ca41eb566df4
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/439693
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

media: vb2: use FOLL_DURABLE and __get_user_pages to avoid CMA migration issues

V4L2 devices usually grab additional references to user pages for a very
long period of time, what causes permanent migration failures if the given
page has been allocated from CMA pageblock. By setting FOLL_DURABLE flag,
videobuf2 will instruct __get_user_pages() to migrate user pages out of
CMA pageblocks before blocking them with an additional reference.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
bug 1517584

Change-Id: Ic59e5219538388604087799dd26217d0ef27d7e4
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/421679
(cherry picked from commit 44a648a412b0733b988a4dad2e14704d1a03190e)
Reviewed-on: http://git-master/r/421585
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

mm: get_user_pages: migrate out CMA pages when FOLL_DURABLE flag is set

When __get_user_pages() is called with FOLL_DURABLE flag,
ensure that no page in CMA pageblocks gets locked.
This workarounds the permanent migration failures caused
by locking the pages by get_user_pages() call for a long
period of time.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
bug 1517584

Change-Id: I11b7c87e78f1022d6fded85a1ed6bac73c5f0a7c
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/421678
(cherry picked from commit e032a2e8d2604e150cb610562c3c457b91050d56)
Reviewed-on: http://git-master/r/421584
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

mm: get_user_pages: use NON-MOVABLE pages when FOLL_DURABLE flag is set

Ensure that newly allocated pages, which are faulted in
in FOLL_DURABLE mode comes from non-movalbe pageblocks,
to workaround migration failures with CMA

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
bug 1517584

Change-Id: I76d2185cc7e77992db585a71efaa06a5c0105a76
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/421677
(cherry picked from commit 0e7370ef6597150986099c837b26ccb526f1ac4a)
Reviewed-on: http://git-master/r/421582
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

mm: get_user_pages: use static inline

__get_user_pages() is already exported function,
so get_user_pages() can be easily inlined to the
caller functions.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
bug 1517584

Change-Id: If700fa3c6ead133299fa99a702887584b76e5ffb
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/421676
(cherry picked from commit de6afd3c6591b73bc81d8ebd77edc74e884c22d0)
Reviewed-on: http://git-master/r/421578
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

mm: introduce migrate_replace_page() for migrating page to the given target

introduce migrate_replace_page for migrating
page to the given target

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
bug 1517584

Change-Id: I5f1d3bcb19ca7d9c9cf7234e8d3472a42c4f40af
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/421675
(cherry picked from commit dfb505aca91ae0e976e4e2614aaae5e293d68f05)
Reviewed-on: http://git-master/r/420650
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: tegra: vcm30t124: remove register pca9539 addr 75

Register of pca9539 for client address 75 is moved to dt,
using http://git-master/r/#/c/436600
So, removing from platfrom register.

bug 1426938

Change-Id: I6be3b0dee7338c768f8447743bcc400001df77ac
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/437663
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

arm: config: vcm30t124: Enable BT related defconfig's

Enable BT specific defconfig
CONFIG_BT_HCIUART
CONFIG_BT_HCIUART_H4
CONFIG_BT_RFCOMM

bug 1426938

Change-Id: I7740e127860048e07fe4b01e192cda2436803462
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/432994
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

mmc: tegra: add DQS trim delay member

-Added DQS trim delay member in platform data
-Parse DQS trim delay member in the driver
-Update DQS trim val register for eMMC HS400 mode only.

Bug 1475512

Change-Id: If07e9d6ad27a0081159766968a0afc07046ec3bc
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/422175
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM64: DT: Add SDHCI DT support for T210 platforms

-Add SDHCI DT support changes for T210 platforms E2190 and E2220
boards.

Change-Id: I66d42e968fbc053abeda0041b2dc12508dc3cfdd
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/436131
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

video: tegra: host: remove gpu edp references

For gk20a, gpu_edp flag was used to inform edp to update load.
As gpu code isolated from nvhost, remove reference.

Change-Id: Iee3224cc346f0041f58115da99d7192296fdf2d9
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/439797
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

video: tegra: hdmi: clk support

- safe clk config
- macro clk config

Bug 200006291

Change-Id: Id00f56d94be703fa77774b8ae7282a9e22d2a2e1
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/437193
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

video: tegra: host: Fix channel refcount issues

This patch fixes few possible races in channel initialisation and
deinitialisation:
- If two channel initialisations were running concurrently for
the same device and the first initialisation failed, we potentially
gave an uninitialised channel to the second requester
- If putchannel() triggered uninitialisation, we were still able
to give the channel in getchannel().

Bug 200013323

Change-Id: I99fa726db99fbb98401d5703cc2572131907f726
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/437726
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

trace: events: dma: add tracing for alloc_attrs and free_attrs

Add tracing for dma_alloc_attrs and dma_free_attrs.

Change-Id: Ib93964a1cf13412cbe32f989dc938b8cfc89c75b
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/411068

Arm: tegra: Enable UHS-1 mode for SDMMC1

bug 1457466

Change-Id: I1d08eb0f5cc17ef92fffb06cc8b1e3458a747a43
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/421973
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

net: wireless: remove bcm43241 and 43341 folders

BCM43241 and BCM43341 folders in drivers/net/wiress/ are symlinks
code of BCMDHD with specific config options.
These folders are no longer needed as the same is handled in bcmdhd.

Bug 200013167

Change-Id: Ib5b09dab7cc7a88036359870c42a025feeb16d87
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/423611
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Tested-by: Seshagiri Holi <sholi@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

Arm: tegra: vcm30t124: Register sdhci.0 using TEGRA_WIFI_ENABLE

board-vcm30t124-sdhci.c will compile
only when CONFIG_TEGRA_WIFI_ENABLE is defined.

bug 1453989
bug 200013167

Change-Id: I146ea263c9f973af3c8a05ddc26a89cdf273e29f
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/423507
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

Arm: Tegra: register wifi with TEGRA_WIFI_ENABLE

register wifi only when CONFIG_TEGRA_WIFI_ENABLE,
config is defined.

This change is require until bcmdhd driver
moved to DT

bug 1453989
bug 200013167

Change-Id: I944a3e48cc3e37c0450f5a176e866f94725e2139
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/423506
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

pinctrl: tegra124: correct pin group names

Correct the sequence of port c4 and c5 to fix register offset.

Bug 1532280

Change-Id: I95ab43e036ef9ccfdf535951fb00ea388b60974d
Signed-off-by: Steve Kuo <stevek@nvidia.com>
Reviewed-on: http://git-master/r/439775
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: dt: add dt node for pca9539 & bluedroid_pm

- add support for 1860 board in dt
- Add dt node for pca9539 for address 75
- Add dt node for bluedroid_pm which use pca9539 GPIO lines.
rfkill driver is not DT enabled, so we are using bluedroid_pm

bug 1426938

Change-Id: I6496faf631b0bc71b5aac6af8e1ad1edeb0649f8
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/436600
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: dts: pass pll parent for sdhci

pass selectable parent list for sdhci through dt

Bug 200011673

Change-Id: I04a40bfaeadf4d0dc4989cff0527a8c7162d45bd
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/438261
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: dts: Add vmmc regulator in dt

sdhci-tegra driver doesn’t require vmmc regulator,
As DUMMY_REGULATOR is defined for automotive
platform we see OCR errors. If we define a fixed regulator
for vmmc this error log will not be reported.

bug 200010723

Change-Id: Icc1886bcee927def4eab3b72cdcea862401da79b
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/438085
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

pinctrl: remove unused tegra specific pinmux header

Change-Id: I6a2a9ae53d77206f0fd5db7e9bdd5c6e023005af
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/437725

Doc: DT: Add DT binding doc for Maxim 77620 thermal driver

Bug 1477154

Change-Id: I64403a5da74d80fd3a370da2320b95e155a24d31
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/437686
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

media: camera: get rid of pinmux configuration

Get rid of pinmux configuration through legacy pinmux apis.

Change-Id: Iadec0f5284c567a07544cab208334eabada5c0a8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/437722
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

ARM: tegra: add power tree dtsi file for E2174 power tree

Add power tree dtsi file on which all drivers will add theit regulator
handles.

This will help to put all regulators entry on one place rather than
scattering them on multiple places.

Change-Id: I78d0f6f8bc1def1e5151d6ca3fced9b1e1ed7ee8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/438660

ARM: tegra: correct regulator handle for T210 ERS interposer

Change-Id: Ib2e724c3a0b1beb3d33064270edbefab9074850d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/438659

pinctr: tegra: get rid of pinctrl tegra header

This header is no more used in driver and hence removing
the include.

Change-Id: I46b8dab265499d406ba815894fb8c90c73f32d63
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/437723
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

sdhci: tegra: no need to check maximum value of pull up strength

As pinctrl framework already put the checks for requested pull up
strength and set it to maximum supported value, there is no need
to have similar checks on client side.

Removing this extra check.

Change-Id: I45df66958edb4845d5e05c53e8348b940dfd0ee2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/437724
GVS: Gerrit_Virtual_Submit

pinctrl: tegra: set maximum value of pull up strength if requested more

If client request the pull up strenght more than supported value then
set it to maximum supported value.

Change-Id: I1bdc9375026a28c69b21c330863ecbfbd820c803
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/438102
GVS: Gerrit_Virtual_Submit

ARM: tegra: remove platform device entry for gpio, pincntrl, apbdma, mipi

Remove the platform device entries for gpio, pincontrol, apb dma
and mipi as these are regsitered from DTS.

Change-Id: I949fba69b0d9a0cf7d87b537c93d2ce8119ac80a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/438120
GVS: Gerrit_Virtual_Submit

ARM: tegra: dvfs: Use regulator-name property

Used regulator-name property for dvfs rail alignment instead of
regulator-consumer-supply property.

Bug 1259555

Change-Id: I81b8c320ef7011a7673585869f79ff3e828465c4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/438553
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM64: tegra: Remove VDD_CPU consumer-supply property

Removed regulator-consumer-supply property from vdd_cpu regulator.
Changed regulators name to specify supplied rail, instead.

Bug 1529555

Change-Id: If2ef4741f983d4015bf6e46557cebc58d17d622d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/438552
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Update dev_id for xusb clocks

Update dev_id for xusb_dev, xusb_dev_src, xusb_ss_src,
xusb_hs_src, xusb_ss, xusb_fs_src

Change-Id: I5af8da624ee46a9a1e4c29a6535dcbcb30c620ca
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/438269
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM64: tegra: Re-named DFLL dtsi file.

Renamed:
tegra210-platforms/tegra210-ers-e2174-dfll-pwm.dtsi
to
tegra210-platforms/tegra210-ers-dfll-e2174-1101-a00.dtsi
(replaced pwm designation with board sku).

Bug 1529555

Change-Id: Id76e541662bd38d48f0c4a4ee0e9dc4444b51f0b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/438551
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

gpu: Split clk_ops for GK20A and GM20B

Split clk_ops for GK20A and GM20B into different files

Bug 1450787

Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/437771
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Fix PLL fractional dividers range

The SDM setting on Tegra21 PLLs with fractional dividers is 16-bit
signed 2's complement integer, with 13-bit valid range (-4096...4095).
The setting is represented in PLL data structure as 16-bit unsigned
non-zero integer. The latter restriction is applied to indicate that
SDM is disabled when SDM data is zero. Current code decrements feedback
divider by one to assure non-zero SDM data. This pushes SDM setting
above valid range.

Fixed it by removing decrement and keeping SDM data equal to SDM
settings, with the exception of 0-setting that is mapped to maximum
possible 0xFFFF data value (never overlaps with valid setting).

Respectively updated PLL frequency tables, and name of SDM field in
PLL object structure.

Bug 1413190

Change-Id: I3c3f69734c31069aa0b74eef84e0f7bbf7a72283
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/439699
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arm64: dts: add TegraSim variant of T132 Norrin

Add a new board variart for TegraSim. This inherits the most of the
common Norrin files but disables some features.

Change-Id: I3373d6b208b3abba88fda8bdaa0b15884093d937
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/438827
Tested-by: Mark Young <myoung@nvidia.com>

arm64: tegra: remove obsolete sensor for T210ref

Clean up Sensors (ACC, gyro, compass, bmp, ALS) from board-file.

Bug 200020855

Change-Id: Ia9b9743420682f182e3a1a6ee22d80447713e61f
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/437591
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

ARM: tegra: Switch AS364x strobe mode to i2c

AS364x flash driver is now triggered through
i2c, switching the kernel driver to support
this.

Bug 200000268

Change-Id: I62d1b05eca3d4bdada98bed85170cc1bcee87cf2
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/437802
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sean Pieper <spieper@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

platform: tegra: nvadsp: ADSP app allocation

ADSP app needs to be in the range of +/-32MB. Hence the memory needed for app
loading needs to pre-allocated and managed. Using the generic mem manager to
manage the app loading memory.

Bug 200009740
Bug 200006129

Change-Id: I02ec660a80783da9a0d4e0ec21b5a61e370c9b8a
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/438282
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

gpu: nvgpu: Use 1kHz resolution for GPCPLL programming

Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming:
limits specifications, calculating GPCPLL settings, storing target
frequency values, and proving output from debug monitor. Updated
comments in clock header to properly reflect frequency units.

Bug 1450787

Change-Id: Ica58f794b82522288f2883c40626d82dbd794902
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437943
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Allow BPMP to control SCLK skipper

SCLK skipper will be owned by BPMP f/w. Hence, delegated skipper
register update to BPMP via respective IPC.

Bug 1386253
Bug 1413190

Change-Id: I1dc69399ac854637c2affe87a2c97c0b223fcc99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437822
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Update CBUS skipper operations

- Modified skipper initialization to always set 1:1 ratio.
- Added SHARED_BUS_USE_SKIPPERS flag, and engage skippers only if it
  is set.
- Set SHARED_BUS_USE_SKIPPERS flag for c2bus and c3bus provided
  TEGRA_CBUS_CAN_USE_SKIPPERS configuration option is selected.
- Installed all Tegra21 module skippers (added VI and ISP skippers,
  restored TSEC skipper).

Bug 1413190

Change-Id: Ie747fcc427fe9fb195daa8fddb8034ee2c1872a3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437821
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

tegra21: Add TEGRA_CBUS_CAN_USE_SKIPPERS option

Added TEGRA_CBUS_CAN_USE_SKIPPERS configuration option. When enabled,
clock skippers for cbus modules can be used to provide fine granularity
clock rate control. Disabled by default.

Bug 1413190

Change-Id: I2d8086967915f9dee6a2a290f24ee9a680268f54
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437820
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Set PCLK clock boot floor

Set APB clock floor (effectively HCLK and SCLK floor as well) at 136MHz
during boot until all system bus clients have a chance to request rate.

Bug 1413190

Change-Id: Ia01bb244cfd9c339661118cab2f72c6956de54d5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437819
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: Update PLLC4 usage policy

- Set maximum PLLC4_OUT0 frequency in PLLC4 default configuration to
provide better scaling granularity for downstream clients
- Set PLLC4_OUT0 as high pll source for SCLK (instead of PLLC4_OUT1),
and host1x (instead of PLLC). Increased maximum clock limit for SCLK
mux to allow high PLLC4 rate.
- Added PLLC4_OUT0 to DVFS table

Bug 1413190

Change-Id: I38cf4c04d18f5b0814417a24509c16b7fedbefda
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437818
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

usb: gadget: tcm: Fix UASP workqueues usage

In some error scenario's the UASP drivers only worker thread
doesnt resume properly from sleep causing the failure of all
later data transfers.

Bug 1454751

Change-Id: I885df07c9a0d632a2e043beb7b1a73e4fc50ef96
Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Reviewed-on: http://git-master/r/413486
Reviewed-by: David Lim <dlim@nvidia.com>
Reviewed-by: Hui Fu <hfu@nvidia.com>
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: tcm: get_alt function in UASP

Implemented the missing get_alt function in UASP gadget
that gets called when the HOST sends a GET_INTERFACE request

Bug 1482184

Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Change-Id: Id001b299f6ebd41eb9b7eff34a656ec9581d7173
Reviewed-on: http://git-master/r/385825
Reviewed-by: Hui Fu <hfu@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439474
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: tcm: UASP Task Managemnt/Response IU

Current UASP driver doesn't implement handling task management and
response IU's because of which some of the compliance tests are
failing. Have added code for that

Bug 1411411

Change-Id: I867970c22e34e6ef46f12865f96e5cf3e285b9b5
Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Reviewed-on: http://git-master/r/364264
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439467
Reviewed-by: Automatic_Commit_Validation_User

usb: gadget: f_fs choose right descriptors

Use config_ep_by_speed() to choose right descriptors for an endpoint
according to gadget speed

Change-Id: I1a2f3098744567a1b65dedec3ea3c7a1b9992634
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439438
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: tcm: Fix UASP enumeration issue

Currently the same endpoint descriptor
is used in the configuration descriptor
(uasp_ss_function_desc) for  both the BOT and
UASP. So in the init when we call the
usb_ep_autoconfig_ss, the address is set in the
uasp_ss_*_desc common descriptor. Later when we
try to configure the ep by calling
config_ep_by_speed,it matches the command ep
descriptor of BOT in the configuration descriptor
and uses the next bot’s companion descriptor that
doesn’t have the streams enabled. Because of
using this wrong descriptor the UASP is not
getting enumerated.

Change-Id: I72da7ed13b738498b2427bfe9a4e4e101d49cddf
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439409
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: fmtp: add super speed support

Change-Id: Ia8c4438d4522a5e4304d3689e17a1c1a124fc919
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/439408
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: tegra_xudc: Enable XUSB device mode

1. Enable XUSB device mode as a module in defconfig.
2. Hack pad programming proved to be working on fpga.
3. vbus sense and termination required for fpga

Change-Id: I6a7ec71a481d1c41456fc1f45364a5a54d5a5692
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/438520
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

arm: tegra: rearrange throttlectl code to be symmetric

Throttlectl code for CPU and GPU are similar, but were coded
differently. Rearranged code so the similarity is highlighted.

Also moved configuring the level in CCROC NV_THERM out of level
selection. This impacts how board-files configure throttling.

This will be fully resolved once we move to device-tree to configure
all thermal management configuration.

Bug 200004664

Change-Id: I0a34a8fe7e38129bfef637f1664b716624ae7af1
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/439422
GVS: Gerrit_Virtual_Submit

ARM: T132: DVFS: Increase cpu frequency granularity below vmin

Granularity set at 25.5mhz upto 1020Mhz.

Bug 1509711

Change-Id: I80d4e78a2c8d1fe995a88ed220b7831b500e162f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/417245
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
Reviewed-on: http://git-master/r/432803
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

video: tegra: host: remove vi-i2c reference.

 vi-i2c platform data no more used in nvhost driver.
So remove device data declaration.

Change-Id: I1752679b05a5218af0f664ebbcba52210b65f446
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/438051
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

arm: tegra: platsmp: fix smp_processor_id

This fix replaces smp_processor_id with raw_smp_processor_id
in tegra30_power_up_cpu and tegra11x_power_up_cpu. Gets rid
of extraneous warning message.

Bug 1527084

Change-Id: Ibfba094d89eb26fdc93be45a409fb670eac92698
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: http://git-master/r/427260
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

arm64: dts: Add fixed regulator for Grenada

To disable dummy regulator, added power tree
entries under fixed regulator so that there will
not be any regulator_get failures.

Change-Id: I7933de623230d19f9676cc922fe64d4451ced62f
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/438787
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm64: tegra: dts: Add pca9539 with 7h'74 and 7h'75 to e2141

Added pca9539 devices with address 7h'74 and 7h'75
to E2141 platform.

Change-Id: Id364fa17d43e966c1c8070cbea19903e135fb55f
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/438505
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: add power tree file for PM375 based system

Add power tree dtsi file for PM375 based PMIC module and include this
from all top level DTS files. Also add the required regulator handles
for drivers which is registered from DT. Delete the non-required
regulators consumer/supply if the client is from DT.

Change-Id: I39fdafdeccbe65b74d22d495e7e206ed6b3d1dd0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: add power tree file for PM359 based system

Add power tree dtsi file for PM359 based PMIC module and include this
from all top level DTS files. Also add the required regulator handles
for drivers which is registered from DT. Delete the non-required
regulators consumer/supply if the client is from DT.

Change-Id: Idb713e8d347f3d119c4e7adb5a444015cfef545f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: add power tree file for Norrin based system

Add power tree dtsi file for Norrin based PMIC module and include this
from all top level DTS files. Also add the required regulator handles
for drivers which is registered from DT. Delete the non-required
regulators consumer/supply if the client is from DT.

Change-Id: I4cd97b33e8f118f1606f3cf0e3dea033924f315c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>