gpu:nvgpu:fix powergate disabling order

ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine

Bug 200013495
Bug 200014542

Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/432206
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Shih <rshih@nvidia.com>
Tested-by: Robert Shih <rshih@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index ffd7ec083d951568bd74fac217662bb22ba37531..a373dacc27b31192c2710349dd0bc12cafc1ec73 100644 (file)
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -560,6 +560,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
                        if (err)
                                return -EPERM;
 
+                       /*do elpg disable before clock gating disable*/
+                       gk20a_pmu_disable_elpg(g);
                        g->ops.clock_gating.slcg_gr_load_gating_prod(g,
                                        false);
                        g->ops.clock_gating.slcg_perf_load_gating_prod(g,
@@ -570,7 +572,6 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
                        gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A);
                        gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A);
 
-                       gk20a_pmu_disable_elpg(g);
                }
 
                dbg_s->is_pg_disabled = true;