From: Vijayakumar Date: Fri, 27 Jun 2014 09:20:31 +0000 (+0530) Subject: gpu:nvgpu:fix powergate disabling order X-Git-Tag: daily-2014.07.30.0_rel-st8-r2.2-partner~50 X-Git-Url: https://rtime.felk.cvut.cz/gitweb/sojka/nv-tegra/linux-3.10.git/commitdiff_plain/84032884e16c4b1a5f925845078286c438c19c17 gpu:nvgpu:fix powergate disabling order ELPG has to disabled before we write to clock gating registers If ELPG is engaged during clock gating register write it will cause error in ELPG engine Bug 200013495 Bug 200014542 Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/432206 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Robert Shih Tested-by: Robert Shih Reviewed-by: Mitch Luban --- diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index ffd7ec083d9..a373dacc27b 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c @@ -560,6 +560,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, if (err) return -EPERM; + /*do elpg disable before clock gating disable*/ + gk20a_pmu_disable_elpg(g); g->ops.clock_gating.slcg_gr_load_gating_prod(g, false); g->ops.clock_gating.slcg_perf_load_gating_prod(g, @@ -570,7 +572,6 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A); gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A); - gk20a_pmu_disable_elpg(g); } dbg_s->is_pg_disabled = true;