drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * Copyright (C) 2010-2016 NVIDIA Corporation.  All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/i2c.h>
  26 #include <linux/i2c-algo-bit.h>
  27 #include <linux/i2c-gpio.h>
  28 #include <linux/io.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/gpio.h>
  31 #include <linux/delay.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c-tegra.h>
  35 #include <linux/of_device.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/of_i2c.h>
  38 #include <linux/module.h>
  39 #include <linux/clk/tegra.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/clk/tegra.h>
  42 #include <linux/tegra-pm.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/pinctrl/pinconf-tegra.h>
  45 #include <linux/tegra_prod.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #define TEGRA_I2C_TIMEOUT                       (msecs_to_jiffies(1000))
  50 #define TEGRA_I2C_RETRIES                       3
  51 #define BYTES_PER_FIFO_WORD                     4
  52
  53 #define I2C_CNFG                                0x000
  54 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  55 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  56 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  57 #define I2C_CNFG_MULTI_MASTER_MODE              (1<<17)
  58 #define I2C_STATUS                              0x01C
  59 #define I2C_STATUS_BUSY                         (1<<8)
  60 #define I2C_SL_CNFG                             0x020
  61 #define I2C_SL_CNFG_NACK                        (1<<1)
  62 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  63 #define I2C_SL_ADDR1                            0x02c
  64 #define I2C_SL_ADDR2                            0x030
  65 #define I2C_TX_FIFO                             0x050
  66 #define I2C_RX_FIFO                             0x054
  67 #define I2C_PACKET_TRANSFER_STATUS              0x058
  68 #define I2C_FIFO_CONTROL                        0x05c
  69 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  70 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  71 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  72 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  73 #define I2C_FIFO_STATUS                         0x060
  74 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  75 #define I2C_FIFO_STATUS_TX_SHIFT                4
  76 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  77 #define I2C_FIFO_STATUS_RX_SHIFT                0
  78 #define I2C_INT_MASK                            0x064
  79 #define I2C_INT_STATUS                          0x068
  80 #define I2C_INT_BUS_CLEAR_DONE          (1<<11)
  81 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  82 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  83 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  84 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  85 #define I2C_INT_NO_ACK                          (1<<3)
  86 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  87 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  88 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  89
  90 #define I2C_CLK_DIVISOR                         0x06c
  91 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  92 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  93
  94 #define DVC_CTRL_REG1                           0x000
  95 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  96 #define DVC_CTRL_REG2                           0x004
  97 #define DVC_CTRL_REG3                           0x008
  98 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  99 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
 100 #define DVC_STATUS                              0x00c
 101 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
 102
 103 #define I2C_ERR_NONE                            0x00
 104 #define I2C_ERR_NO_ACK                          0x01
 105 #define I2C_ERR_ARBITRATION_LOST                0x02
 106 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
 107 #define I2C_ERR_UNEXPECTED_STATUS               0x08
 108
 109 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
 110 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
 111 #define PACKET_HEADER0_CONT_ID_SHIFT            12
 112 #define PACKET_HEADER0_CONT_ID_MASK             0xF
 113 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
 114
 115 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
 116 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
 117 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
 118 #define I2C_HEADER_READ                         (1<<19)
 119 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
 120 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 121 #define I2C_HEADER_REPEAT_START                 (1<<16)
 122 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 123 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 124 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 125
 126 #define I2C_BUS_CLEAR_CNFG                              0x084
 127 #define I2C_BC_SCLK_THRESHOLD                           (9<<16)
 128 #define I2C_BC_STOP_COND                                (1<<2)
 129 #define I2C_BC_TERMINATE                                (1<<1)
 130 #define I2C_BC_ENABLE                                   (1<<0)
 131
 132 #define I2C_BUS_CLEAR_STATUS                            0x088
 133 #define I2C_BC_STATUS                                   (1<<0)
 134
 135 #define I2C_CONFIG_LOAD                         0x08C
 136 #define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
 137 #define I2C_SLV_CONFIG_LOAD                     (1 << 1)
 138 #define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
 139
 140 #define I2C_CLKEN_OVERRIDE                      0x090
 141 #define I2C_MST_CORE_CLKEN_OVR                  (1 << 0)
 142
 143 #define SL_ADDR1(addr) (addr & 0xff)
 144 #define SL_ADDR2(addr) ((addr >> 8) & 0xff)
 145
 146 #define MAX_BUSCLEAR_CLOCK                      (9 * 8 + 1)
 147 #define I2C_MAX_TRANSFER_LEN                    4096
 148 /*
 149  * msg_end_type: The bus control which need to be send at end of transfer.
 150  * @MSG_END_STOP: Send stop pulse at end of transfer.
 151  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 152  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 153  *              stop or repeat start.
 154  */
 155 enum msg_end_type {
 156         MSG_END_STOP,
 157         MSG_END_REPEAT_START,
 158         MSG_END_CONTINUE,
 159 };
 160
 161 struct tegra_i2c_chipdata {
 162         bool timeout_irq_occurs_before_bus_inactive;
 163         bool has_xfer_complete_interrupt;
 164         bool has_hw_arb_support;
 165         bool has_fast_clock;
 166         bool has_clk_divisor_std_fast_mode;
 167         bool has_continue_xfer_support;
 168         u16 clk_divisor_std_fast_mode;
 169         u16 clk_divisor_fast_plus_mode;
 170         u16 clk_divisor_hs_mode;
 171         int clk_multiplier_hs_mode;
 172         bool has_config_load_reg;
 173         bool has_multi_master_en_bit;
 174         bool has_clk_override_reg;
 175 };
 176
 177 /**
 178  * struct tegra_i2c_dev - per device i2c context
 179  * @dev: device reference for power management
 180  * @adapter: core i2c layer adapter information
 181  * @div_clk: clock reference for div clock of i2c controller.
 182  * @fast_clk: clock reference for fast clock of i2c controller.
 183  * @base: ioremapped registers cookie
 184  * @cont_id: i2c controller id, used for for packet header
 185  * @irq: irq number of transfer complete interrupt
 186  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 187  * @msg_complete: transfer completion notifier
 188  * @msg_err: error code for completed message
 189  * @msg_buf: pointer to current message data
 190  * @msg_buf_remaining: size of unsent data in the message buffer
 191  * @msg_read: identifies read transfers
 192  * @bus_clk_rate: current i2c bus clock rate
 193  * @is_suspended: prevents i2c controller accesses after suspend is called
 194  */
 195 struct tegra_i2c_dev {
 196         struct device *dev;
 197         struct i2c_adapter adapter;
 198         struct clk *div_clk;
 199         struct clk *fast_clk;
 200         bool needs_cl_dvfs_clock;
 201         struct clk *dvfs_ref_clk;
 202         struct clk *dvfs_soc_clk;
 203         spinlock_t fifo_lock;
 204         spinlock_t mem_lock;
 205         void __iomem *base;
 206         int cont_id;
 207         int irq;
 208         bool irq_disabled;
 209         int is_dvc;
 210         struct completion msg_complete;
 211         int msg_err;
 212         int next_msg_err;
 213         u8 *msg_buf;
 214         u8 *next_msg_buf;
 215         u32 packet_header;
 216         u32 next_packet_header;
 217         u32 payload_size;
 218         u32 next_payload_size;
 219         u32 io_header;
 220         u32 next_io_header;
 221         size_t msg_buf_remaining;
 222         size_t next_msg_buf_remaining;
 223         int msg_read;
 224         int next_msg_read;
 225         struct i2c_msg *msgs;
 226         int msg_add;
 227         int next_msg_add;
 228         int msgs_num;
 229         unsigned long bus_clk_rate;
 230         bool is_suspended;
 231         u16 slave_addr;
 232         bool is_clkon_always;
 233         bool is_interruptable_xfer;
 234         bool is_high_speed_enable;
 235         u16 hs_master_code;
 236         u16 clk_divisor_non_hs_mode;
 237         bool use_single_xfer_complete;
 238         const struct tegra_i2c_chipdata *chipdata;
 239         int scl_gpio;
 240         int sda_gpio;
 241         struct i2c_algo_bit_data bit_data;
 242         const struct i2c_algorithm *bit_algo;
 243         bool bit_banging_xfer_after_shutdown;
 244         bool is_shutdown;
 245         struct notifier_block pm_nb;
 246         struct tegra_prod_list *prod_list;
 247         bool is_multimaster_mode;
 248 };
 249
 250 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 251 {
 252         writel(val, i2c_dev->base + reg);
 253 }
 254
 255 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 256 {
 257         return readl(i2c_dev->base + reg);
 258 }
 259
 260 static void dvc_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 261 {
 262         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 263         int_mask &= ~mask;
 264         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
 265 }
 266
 267 static void dvc_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 268 {
 269         u32 int_mask = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 270         int_mask |= mask;
 271         dvc_writel(i2c_dev, int_mask, DVC_CTRL_REG3);
 272 }
 273
 274 /*
 275  * i2c_writel and i2c_readl will offset the register if necessary to talk
 276  * to the I2C block inside the DVC block
 277  */
 278 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 279         unsigned long reg)
 280 {
 281         if (i2c_dev->is_dvc)
 282                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 283         return reg;
 284 }
 285
 286 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 287         unsigned long reg)
 288 {
 289         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 290
 291         /* Read back register to make sure that register writes completed */
 292         if (reg != I2C_TX_FIFO)
 293                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 294 }
 295
 296 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 297 {
 298         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 299 }
 300
 301 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 302         unsigned long reg, int len)
 303 {
 304         u32 *buf = data;
 305         unsigned long flags = 0;
 306
 307         if (!i2c_dev->is_interruptable_xfer)
 308                 spin_lock_irqsave(&i2c_dev->mem_lock, flags);
 309
 310         while (len--)
 311                 writel(*buf++, i2c_dev->base +
 312                                         tegra_i2c_reg_addr(i2c_dev, reg));
 313
 314         if (!i2c_dev->is_interruptable_xfer)
 315                 spin_unlock_irqrestore(&i2c_dev->mem_lock, flags);
 316 }
 317
 318 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 319         unsigned long reg, int len)
 320 {
 321         u32 *buf = data;
 322         unsigned long flags = 0;
 323
 324         if (!i2c_dev->is_interruptable_xfer)
 325                 spin_lock_irqsave(&i2c_dev->mem_lock, flags);
 326
 327         while (len--)
 328                 *buf++ = readl(i2c_dev->base +
 329                                         tegra_i2c_reg_addr(i2c_dev, reg));
 330
 331         if (!i2c_dev->is_interruptable_xfer)
 332                 spin_unlock_irqrestore(&i2c_dev->mem_lock, flags);
 333 }
 334
 335 static inline void tegra_i2c_gpio_setscl(void *data, int state)
 336 {
 337         struct tegra_i2c_dev *i2c_dev = data;
 338
 339         gpio_set_value(i2c_dev->scl_gpio, state);
 340 }
 341
 342 static inline int tegra_i2c_gpio_getscl(void *data)
 343 {
 344         struct tegra_i2c_dev *i2c_dev = data;
 345
 346         return gpio_get_value(i2c_dev->scl_gpio);
 347 }
 348
 349 static inline void tegra_i2c_gpio_setsda(void *data, int state)
 350 {
 351         struct tegra_i2c_dev *i2c_dev = data;
 352
 353         gpio_set_value(i2c_dev->sda_gpio, state);
 354 }
 355
 356 static inline int tegra_i2c_gpio_getsda(void *data)
 357 {
 358         struct tegra_i2c_dev *i2c_dev = data;
 359
 360         return gpio_get_value(i2c_dev->sda_gpio);
 361 }
 362
 363 static int tegra_i2c_gpio_request(struct tegra_i2c_dev *i2c_dev)
 364 {
 365         int ret;
 366
 367         ret = gpio_request_one(i2c_dev->scl_gpio,
 368                                 GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN,
 369                                 "i2c-gpio-scl");
 370         if (ret < 0) {
 371                 dev_err(i2c_dev->dev, "GPIO request for gpio %d failed %d\n",
 372                                 i2c_dev->scl_gpio, ret);
 373                 return ret;
 374         }
 375
 376         ret = gpio_request_one(i2c_dev->sda_gpio,
 377                                 GPIOF_OUT_INIT_HIGH | GPIOF_OPEN_DRAIN,
 378                                 "i2c-gpio-sda");
 379         if (ret < 0) {
 380                 dev_err(i2c_dev->dev, "GPIO request for gpio %d failed %d\n",
 381                                 i2c_dev->sda_gpio, ret);
 382                 gpio_free(i2c_dev->scl_gpio);
 383                 return ret;
 384         }
 385         return ret;
 386 }
 387
 388 static void tegra_i2c_gpio_free(struct tegra_i2c_dev *i2c_dev)
 389 {
 390         gpio_free(i2c_dev->scl_gpio);
 391         gpio_free(i2c_dev->sda_gpio);
 392 }
 393
 394 static int tegra_i2c_gpio_xfer(struct i2c_adapter *adap,
 395         struct i2c_msg msgs[], int num)
 396 {
 397         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 398         int ret;
 399
 400         ret = tegra_i2c_gpio_request(i2c_dev);
 401         if (ret < 0)
 402                 return ret;
 403
 404         ret = i2c_dev->bit_algo->master_xfer(adap, msgs, num);
 405         if (ret < 0)
 406                 dev_err(i2c_dev->dev, "i2c-bit-algo xfer failed %d\n", ret);
 407
 408         tegra_i2c_gpio_free(i2c_dev);
 409         return ret;
 410 }
 411
 412 static int tegra_i2c_gpio_init(struct tegra_i2c_dev *i2c_dev)
 413 {
 414         struct i2c_algo_bit_data *bit_data = &i2c_dev->bit_data;
 415
 416         bit_data->setsda = tegra_i2c_gpio_setsda;
 417         bit_data->getsda = tegra_i2c_gpio_getsda;
 418         bit_data->setscl = tegra_i2c_gpio_setscl;
 419         bit_data->getscl = tegra_i2c_gpio_getscl;
 420         bit_data->data = i2c_dev;
 421         bit_data->udelay = 20; /* 50KHz */
 422         bit_data->timeout = HZ; /* 10 ms*/
 423         i2c_dev->bit_algo = &i2c_bit_algo;
 424         i2c_dev->adapter.algo_data = bit_data;
 425         return 0;
 426 }
 427
 428 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 429 {
 430         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 431         int_mask &= ~mask;
 432         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 433 }
 434
 435 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 436 {
 437         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 438         int_mask |= mask;
 439         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 440 }
 441
 442 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 443 {
 444         unsigned long timeout = jiffies + HZ;
 445         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 446         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 447         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 448
 449         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 450                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 451                 if (time_after(jiffies, timeout)) {
 452                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 453                         return -ETIMEDOUT;
 454                 }
 455                 msleep(1);
 456         }
 457         return 0;
 458 }
 459
 460 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 461 {
 462         u32 val;
 463         int rx_fifo_avail;
 464         u8 *buf = i2c_dev->msg_buf;
 465         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 466         int words_to_transfer;
 467
 468         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 469         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 470                 I2C_FIFO_STATUS_RX_SHIFT;
 471
 472         /* Rounds down to not include partial word at the end of buf */
 473         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 474         if (words_to_transfer > rx_fifo_avail)
 475                 words_to_transfer = rx_fifo_avail;
 476
 477         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 478
 479         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 480         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 481         rx_fifo_avail -= words_to_transfer;
 482
 483         /*
 484          * If there is a partial word at the end of buf, handle it manually to
 485          * prevent overwriting past the end of buf
 486          */
 487         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 488                 BUG_ON(buf_remaining > 3);
 489                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 490                 memcpy(buf, &val, buf_remaining);
 491                 buf_remaining = 0;
 492                 rx_fifo_avail--;
 493         }
 494
 495         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 496         i2c_dev->msg_buf_remaining = buf_remaining;
 497         i2c_dev->msg_buf = buf;
 498         return 0;
 499 }
 500
 501 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 502 {
 503         u32 val;
 504         int tx_fifo_avail;
 505         u8 *buf;
 506         size_t buf_remaining;
 507         int words_to_transfer;
 508
 509         if (!i2c_dev->msg_buf_remaining)
 510                 return 0;
 511         buf = i2c_dev->msg_buf;
 512         buf_remaining = i2c_dev->msg_buf_remaining;
 513
 514         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 515         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 516                 I2C_FIFO_STATUS_TX_SHIFT;
 517
 518         /* Rounds down to not include partial word at the end of buf */
 519         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 520
 521         /* It's very common to have < 4 bytes, so optimize that case. */
 522         if (words_to_transfer) {
 523                 if (words_to_transfer > tx_fifo_avail)
 524                         words_to_transfer = tx_fifo_avail;
 525
 526                 /*
 527                  * Update state before writing to FIFO.  If this casues us
 528                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 529                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 530                  * not maskable).  We need to make sure that the isr sees
 531                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 532                  */
 533                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 534                 tx_fifo_avail -= words_to_transfer;
 535                 i2c_dev->msg_buf_remaining = buf_remaining;
 536                 i2c_dev->msg_buf = buf +
 537                         words_to_transfer * BYTES_PER_FIFO_WORD;
 538                 barrier();
 539
 540                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 541
 542                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 543         }
 544
 545         /*
 546          * If there is a partial word at the end of buf, handle it manually to
 547          * prevent reading past the end of buf, which could cross a page
 548          * boundary and fault.
 549          */
 550         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 551                 if (buf_remaining > 3) {
 552                         dev_err(i2c_dev->dev,
 553                                 "Remaining buffer more than 3 %zd\n",
 554                                 buf_remaining);
 555                         BUG();
 556                 }
 557                 memcpy(&val, buf, buf_remaining);
 558
 559                 /* Again update before writing to FIFO to make sure isr sees. */
 560                 i2c_dev->msg_buf_remaining = 0;
 561                 i2c_dev->msg_buf = NULL;
 562                 barrier();
 563
 564                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 565         }
 566
 567         return 0;
 568 }
 569
 570 /*
 571  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 572  * block.  This block is identical to the rest of the I2C blocks, except that
 573  * it only supports master mode, it has registers moved around, and it needs
 574  * some extra init to get it into I2C mode.  The register moves are handled
 575  * by i2c_readl and i2c_writel
 576  */
 577 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 578 {
 579         u32 val = 0;
 580         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 581         val |= DVC_CTRL_REG3_SW_PROG;
 582         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 583
 584         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 585         val |= DVC_CTRL_REG1_INTR_EN;
 586         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 587 }
 588
 589 static void tegra_i2c_slave_init(struct tegra_i2c_dev *i2c_dev)
 590 {
 591         u32 val = I2C_SL_CNFG_NEWSL | I2C_SL_CNFG_NACK;
 592
 593         i2c_writel(i2c_dev, val, I2C_SL_CNFG);
 594
 595         if (i2c_dev->slave_addr) {
 596                 u16 addr = i2c_dev->slave_addr;
 597
 598                 i2c_writel(i2c_dev, SL_ADDR1(addr), I2C_SL_ADDR1);
 599                 i2c_writel(i2c_dev, SL_ADDR2(addr), I2C_SL_ADDR2);
 600         }
 601 }
 602
 603 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 604 {
 605         int ret;
 606
 607         if (i2c_dev->needs_cl_dvfs_clock) {
 608                 ret = clk_prepare_enable(i2c_dev->dvfs_soc_clk);
 609                 if (ret < 0) {
 610                         dev_err(i2c_dev->dev,
 611                                 "Error in enabling dvfs soc clock %d\n", ret);
 612                         return ret;
 613                 }
 614                 ret = clk_prepare_enable(i2c_dev->dvfs_ref_clk);
 615                 if (ret < 0) {
 616                         dev_err(i2c_dev->dev,
 617                                 "Error in enabling dvfs ref clock %d\n", ret);
 618                         goto ref_clk_err;
 619                 }
 620         }
 621         if (i2c_dev->chipdata->has_fast_clock) {
 622                 ret = clk_prepare_enable(i2c_dev->fast_clk);
 623                 if (ret < 0) {
 624                         dev_err(i2c_dev->dev,
 625                                 "Enabling fast clk failed, err %d\n", ret);
 626                         goto fast_clk_err;
 627                 }
 628         }
 629         ret = clk_prepare_enable(i2c_dev->div_clk);
 630         if (ret < 0) {
 631                 dev_err(i2c_dev->dev,
 632                         "Enabling div clk failed, err %d\n", ret);
 633                 goto div_clk_err;
 634         }
 635         return 0;
 636
 637 div_clk_err:
 638         if (i2c_dev->chipdata->has_fast_clock)
 639                 clk_disable_unprepare(i2c_dev->fast_clk);
 640 fast_clk_err:
 641         if (i2c_dev->needs_cl_dvfs_clock)
 642                 clk_disable_unprepare(i2c_dev->dvfs_ref_clk);
 643 ref_clk_err:
 644         if (i2c_dev->needs_cl_dvfs_clock)
 645                 clk_disable_unprepare(i2c_dev->dvfs_soc_clk);
 646         return ret;
 647 }
 648
 649 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 650 {
 651         clk_disable_unprepare(i2c_dev->div_clk);
 652         if (i2c_dev->chipdata->has_fast_clock)
 653                 clk_disable_unprepare(i2c_dev->fast_clk);
 654         if (i2c_dev->needs_cl_dvfs_clock) {
 655                 clk_disable_unprepare(i2c_dev->dvfs_soc_clk);
 656                 clk_disable_unprepare(i2c_dev->dvfs_ref_clk);
 657         }
 658 }
 659
 660 static int tegra_i2c_set_clk_rate(struct tegra_i2c_dev *i2c_dev)
 661 {
 662         u32 clk_multiplier;
 663         int ret;
 664
 665         if (i2c_dev->is_high_speed_enable)
 666                 clk_multiplier = i2c_dev->chipdata->clk_multiplier_hs_mode
 667                         * (i2c_dev->chipdata->clk_divisor_hs_mode + 1);
 668         else
 669                 clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE
 670                 * (i2c_dev->clk_divisor_non_hs_mode + 1);
 671
 672         ret = clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate
 673                                                         * clk_multiplier);
 674         if (ret < 0) {
 675                 dev_err(i2c_dev->dev, "set clock rate %lu failed: %d\n",
 676                         i2c_dev->bus_clk_rate * clk_multiplier, ret);
 677                 return ret;
 678         }
 679         return ret;
 680 }
 681
 682 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 683 {
 684         u32 val;
 685         int err = 0;
 686         u32 clk_divisor = 0;
 687         unsigned long timeout;
 688
 689         err = tegra_i2c_clock_enable(i2c_dev);
 690         if (err < 0) {
 691                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 692                 return err;
 693         }
 694
 695         tegra_periph_reset_assert(i2c_dev->div_clk);
 696         udelay(2);
 697         tegra_periph_reset_deassert(i2c_dev->div_clk);
 698
 699         if (i2c_dev->is_dvc)
 700                 tegra_dvc_init(i2c_dev);
 701
 702         val = I2C_CNFG_NEW_MASTER_FSM;
 703         if (!i2c_dev->is_high_speed_enable)
 704                 val |= (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 705
 706         i2c_writel(i2c_dev, val, I2C_CNFG);
 707         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 708
 709         err = tegra_i2c_set_clk_rate(i2c_dev);
 710         if (err < 0)
 711                 return err;
 712
 713         clk_divisor |= i2c_dev->chipdata->clk_divisor_hs_mode;
 714         if (i2c_dev->chipdata->has_clk_divisor_std_fast_mode)
 715                 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode
 716                                 << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 717         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 718
 719         if (!i2c_dev->is_dvc) {
 720                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 721                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 722                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 723                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 724                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 725
 726         }
 727
 728         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 729                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 730         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 731
 732         if (!i2c_dev->is_dvc)
 733                 tegra_i2c_slave_init(i2c_dev);
 734
 735         if (tegra_i2c_flush_fifos(i2c_dev))
 736                 err = -ETIMEDOUT;
 737
 738         if (i2c_dev->is_multimaster_mode && i2c_dev->chipdata->has_clk_override_reg)
 739                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 740
 741         if (i2c_dev->chipdata->has_config_load_reg) {
 742                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 743                 timeout = jiffies + msecs_to_jiffies(1000);
 744                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 745                         if (time_after(jiffies, timeout)) {
 746                                 dev_warn(i2c_dev->dev, "timeout waiting for config load\n");
 747                                 return -ETIMEDOUT;
 748                         }
 749                         msleep(1);
 750                 }
 751         }
 752
 753         tegra_prod_set_list(&i2c_dev->base, i2c_dev->prod_list);
 754
 755         tegra_i2c_clock_disable(i2c_dev);
 756
 757         if (i2c_dev->irq_disabled) {
 758                 i2c_dev->irq_disabled = 0;
 759                 enable_irq(i2c_dev->irq);
 760         }
 761
 762         return err;
 763 }
 764 static int tegra_i2c_copy_next_to_current(struct tegra_i2c_dev *i2c_dev)
 765 {
 766         i2c_dev->msg_buf = i2c_dev->next_msg_buf;
 767         i2c_dev->msg_buf_remaining = i2c_dev->next_msg_buf_remaining;
 768         i2c_dev->msg_err = i2c_dev->next_msg_err;
 769         i2c_dev->msg_read = i2c_dev->next_msg_read;
 770         i2c_dev->msg_add = i2c_dev->next_msg_add;
 771         i2c_dev->packet_header = i2c_dev->next_packet_header;
 772         i2c_dev->io_header = i2c_dev->next_io_header;
 773         i2c_dev->payload_size = i2c_dev->next_payload_size;
 774
 775         return 0;
 776 }
 777
 778 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 779 {
 780         u32 status;
 781         unsigned long flags = 0;
 782
 783         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
 784                                         | I2C_INT_TX_FIFO_OVERFLOW;
 785         struct tegra_i2c_dev *i2c_dev = dev_id;
 786         u32 mask;
 787
 788         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 789
 790         if (status == 0) {
 791                 dev_dbg(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
 792                                                 i2c_dev->msg_add);
 793                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 794
 795                 if (!i2c_dev->irq_disabled) {
 796                         disable_irq_nosync(i2c_dev->irq);
 797                         i2c_dev->irq_disabled = 1;
 798                 }
 799                 /* Clear all interrupts */
 800                 status = 0xFFFFFFFFU;
 801                 goto err;
 802         }
 803
 804         if (unlikely(status & status_err)) {
 805                 dev_dbg(i2c_dev->dev, "I2c error status 0x%08x\n", status);
 806                 if (status & I2C_INT_NO_ACK) {
 807                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 808                         dev_dbg(i2c_dev->dev, "no acknowledge from address"
 809                                         " 0x%x\n", i2c_dev->msg_add);
 810                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 811                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 812                 }
 813
 814                 if (status & I2C_INT_ARBITRATION_LOST) {
 815                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 816                         dev_dbg(i2c_dev->dev, "arbitration lost during "
 817                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
 818                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 819                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 820                 }
 821
 822                 if (status & I2C_INT_TX_FIFO_OVERFLOW) {
 823                         i2c_dev->msg_err |= I2C_INT_TX_FIFO_OVERFLOW;
 824                         dev_dbg(i2c_dev->dev, "Tx fifo overflow during "
 825                                 " communicate to add 0x%x\n", i2c_dev->msg_add);
 826                         dev_dbg(i2c_dev->dev, "Packet status 0x%08x\n",
 827                                 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 828                 }
 829                 goto err;
 830         }
 831
 832         if (i2c_dev->chipdata->has_hw_arb_support &&
 833                         (status & I2C_INT_BUS_CLEAR_DONE))
 834                 goto err;
 835
 836         if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
 837                                 && (status == I2C_INT_TX_FIFO_DATA_REQ)
 838                                 && i2c_dev->msg_read
 839                                 && i2c_dev->msg_buf_remaining)) {
 840                 dev_dbg(i2c_dev->dev, "unexpected status\n");
 841                 i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
 842
 843                 if (!i2c_dev->irq_disabled) {
 844                         disable_irq_nosync(i2c_dev->irq);
 845                         i2c_dev->irq_disabled = 1;
 846                 }
 847
 848                 goto err;
 849         }
 850
 851         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 852                 if (i2c_dev->msg_buf_remaining)
 853                         tegra_i2c_empty_rx_fifo(i2c_dev);
 854                 else {
 855                         dev_err(i2c_dev->dev, "--- register dump for buffer remain == 0----\n");
 856                         dev_err(i2c_dev->dev, "I2C_CNFG - 0x%x\n",
 857                                         i2c_readl(i2c_dev, I2C_CNFG));
 858                         dev_err(i2c_dev->dev, "I2C_PACKET_TRANSFER_STATUS - 0x%x\n",
 859                                         i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 860                         dev_err(i2c_dev->dev, "I2C_FIFO_CONTROL - 0x%x\n",
 861                                         i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
 862                         dev_err(i2c_dev->dev, "I2C_FIFO_STATUS - 0x%x\n",
 863                                         i2c_readl(i2c_dev, I2C_FIFO_STATUS));
 864                         dev_err(i2c_dev->dev, "I2C_INT_MASK - 0x%x\n",
 865                                         i2c_readl(i2c_dev, I2C_INT_MASK));
 866                         dev_err(i2c_dev->dev, "I2C_INT_STATUS - 0x%x\n",
 867                                         i2c_readl(i2c_dev, I2C_INT_STATUS));
 868                         dev_err(i2c_dev->dev, "msg_err - 0x%x, msg_read - 0x%x, msg_add - 0x%x\n",
 869                                         i2c_dev->msg_err, i2c_dev->msg_read, i2c_dev->msg_add);
 870                         if (i2c_dev->msgs) {
 871                                 struct i2c_msg *msgs = i2c_dev->msgs;
 872                                 int i;
 873                                 for (i = 0; i < i2c_dev->msgs_num; i++)
 874                                         dev_err(i2c_dev->dev,
 875                                                         "msgs[%d] %c, addr=0x%04x, len=%d\n",
 876                                                         i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
 877                                                         msgs[i].addr, msgs[i].len);
 878                         }
 879                         BUG();
 880                 }
 881         }
 882
 883         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 884                 if (i2c_dev->msg_buf_remaining) {
 885
 886                         if (!i2c_dev->is_interruptable_xfer)
 887                                 spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
 888
 889                         tegra_i2c_fill_tx_fifo(i2c_dev);
 890
 891                         if (!i2c_dev->is_interruptable_xfer)
 892                                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
 893
 894                 }
 895                 else
 896                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 897         }
 898
 899         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 900
 901         if (i2c_dev->is_dvc)
 902                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 903
 904         if (status & I2C_INT_ALL_PACKETS_XFER_COMPLETE) {
 905                 BUG_ON(i2c_dev->msg_buf_remaining);
 906                 complete(&i2c_dev->msg_complete);
 907         } else if ((status & I2C_INT_PACKET_XFER_COMPLETE)
 908                                 && i2c_dev->use_single_xfer_complete) {
 909                 BUG_ON(i2c_dev->msg_buf_remaining);
 910                 complete(&i2c_dev->msg_complete);
 911         }
 912
 913         return IRQ_HANDLED;
 914
 915 err:
 916         dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 917                  i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
 918                  i2c_readl(i2c_dev, I2C_INT_STATUS),
 919                  i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
 920
 921         dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
 922                  i2c_dev->packet_header, i2c_dev->payload_size,
 923                  i2c_dev->io_header);
 924
 925         if (i2c_dev->msgs) {
 926                 struct i2c_msg *msgs = i2c_dev->msgs;
 927                 int i;
 928
 929                 for (i = 0; i < i2c_dev->msgs_num; i++)
 930                         dev_dbg(i2c_dev->dev,
 931                                  "msgs[%d] %c, addr=0x%04x, len=%d\n",
 932                                  i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
 933                                  msgs[i].addr, msgs[i].len);
 934         }
 935
 936         mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 937                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 938                 I2C_INT_RX_FIFO_DATA_REQ | I2C_INT_TX_FIFO_OVERFLOW;
 939
 940         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 941
 942         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
 943                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
 944
 945         if (!(i2c_dev->use_single_xfer_complete &&
 946                         i2c_dev->chipdata->has_xfer_complete_interrupt))
 947                 mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
 948
 949         if (i2c_dev->chipdata->has_hw_arb_support)
 950                 mask |= I2C_INT_BUS_CLEAR_DONE;
 951
 952         /* An error occurred, mask all interrupts */
 953         tegra_i2c_mask_irq(i2c_dev, mask);
 954
 955         /* An error occured, mask dvc interrupt */
 956         if (i2c_dev->is_dvc) {
 957                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
 958                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 959         }
 960
 961         complete(&i2c_dev->msg_complete);
 962
 963         return IRQ_HANDLED;
 964 }
 965
 966 static int tegra_i2c_send_next_read_msg_pkt_header(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *next_msg, enum msg_end_type end_state)
 967 {
 968         i2c_dev->next_msg_buf = next_msg->buf;
 969         i2c_dev->next_msg_buf_remaining = next_msg->len;
 970         i2c_dev->next_msg_err = I2C_ERR_NONE;
 971         i2c_dev->next_msg_read = 1;
 972         i2c_dev->next_msg_add = next_msg->addr;
 973         i2c_dev->next_packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 974                         PACKET_HEADER0_PROTOCOL_I2C |
 975                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 976                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 977
 978         i2c_writel(i2c_dev, i2c_dev->next_packet_header, I2C_TX_FIFO);
 979
 980         i2c_dev->next_payload_size = next_msg->len - 1;
 981         i2c_writel(i2c_dev, i2c_dev->next_payload_size, I2C_TX_FIFO);
 982
 983         i2c_dev->next_io_header = I2C_HEADER_IE_ENABLE;
 984
 985         if (end_state == MSG_END_CONTINUE)
 986                 i2c_dev->next_io_header |= I2C_HEADER_CONTINUE_XFER;
 987         else if (end_state == MSG_END_REPEAT_START)
 988                 i2c_dev->next_io_header |= I2C_HEADER_REPEAT_START;
 989
 990         if (next_msg->flags & I2C_M_TEN) {
 991                 i2c_dev->next_io_header |= next_msg->addr;
 992                 i2c_dev->next_io_header |= I2C_HEADER_10BIT_ADDR;
 993         } else {
 994                 i2c_dev->next_io_header |= (next_msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT);
 995         }
 996         if (next_msg->flags & I2C_M_IGNORE_NAK)
 997                 i2c_dev->next_io_header |= I2C_HEADER_CONT_ON_NAK;
 998
 999         i2c_dev->next_io_header |= I2C_HEADER_READ;
1000
1001         if (i2c_dev->is_high_speed_enable) {
1002                 i2c_dev->next_io_header |= I2C_HEADER_HIGHSPEED_MODE;
1003                 i2c_dev->next_io_header |= ((i2c_dev->hs_master_code & 0x7)
1004                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
1005         }
1006         i2c_writel(i2c_dev, i2c_dev->next_io_header, I2C_TX_FIFO);
1007
1008         return 0;
1009 }
1010
1011 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1012         struct i2c_msg *msg, enum msg_end_type end_state,
1013         struct i2c_msg *next_msg, enum msg_end_type next_msg_end_state)
1014 {
1015         u32 int_mask;
1016         int ret;
1017         unsigned long flags = 0;
1018         unsigned long timeout;
1019         u32 cnfg;
1020         u32 val;
1021
1022         if (msg->len == 0)
1023                 return -EINVAL;
1024
1025         tegra_i2c_flush_fifos(i2c_dev);
1026
1027
1028         i2c_dev->msg_buf = msg->buf;
1029         i2c_dev->msg_buf_remaining = msg->len;
1030         i2c_dev->msg_err = I2C_ERR_NONE;
1031         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1032         INIT_COMPLETION(i2c_dev->msg_complete);
1033
1034         if (!i2c_dev->is_interruptable_xfer)
1035                 spin_lock_irqsave(&i2c_dev->fifo_lock, flags);
1036
1037         cnfg = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
1038         if (i2c_dev->chipdata->has_multi_master_en_bit)
1039                 cnfg |= I2C_CNFG_MULTI_MASTER_MODE;
1040
1041         if (!i2c_dev->is_high_speed_enable)
1042                 cnfg |= (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
1043
1044         i2c_writel(i2c_dev, cnfg, I2C_CNFG);
1045
1046         if (i2c_dev->chipdata->has_config_load_reg) {
1047                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
1048                                         I2C_CONFIG_LOAD);
1049                 timeout = jiffies + msecs_to_jiffies(1000);
1050                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
1051                         if (time_after(jiffies, timeout)) {
1052                                 dev_warn(i2c_dev->dev,
1053                                         "timeout config_load");
1054                                 if (!i2c_dev->is_interruptable_xfer)
1055                                         spin_unlock_irqrestore(&i2c_dev->fifo_lock,
1056                                                                 flags);
1057                                 return -ETIMEDOUT;
1058                         }
1059                         udelay(2);
1060                 }
1061         }
1062         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
1063
1064         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
1065                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
1066         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
1067
1068         i2c_dev->msg_add = msg->addr;
1069
1070         i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1071                         PACKET_HEADER0_PROTOCOL_I2C |
1072                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1073                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1074         i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
1075
1076         i2c_dev->payload_size = msg->len - 1;
1077         i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
1078
1079         i2c_dev->use_single_xfer_complete = true;
1080         i2c_dev->io_header = 0;
1081         if (next_msg == NULL)
1082                 i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
1083
1084         if (end_state == MSG_END_CONTINUE)
1085                 i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
1086         else if (end_state == MSG_END_REPEAT_START)
1087                 i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
1088         if (msg->flags & I2C_M_TEN) {
1089                 i2c_dev->io_header |= msg->addr;
1090                 i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
1091         } else {
1092                 i2c_dev->io_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1093         }
1094         if (msg->flags & I2C_M_IGNORE_NAK)
1095                 i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
1096         if (msg->flags & I2C_M_RD)
1097                 i2c_dev->io_header |= I2C_HEADER_READ;
1098         if (i2c_dev->is_high_speed_enable) {
1099                 i2c_dev->io_header |= I2C_HEADER_HIGHSPEED_MODE;
1100                 i2c_dev->io_header |= ((i2c_dev->hs_master_code & 0x7)
1101                                         <<  I2C_HEADER_MASTER_ADDR_SHIFT);
1102         }
1103         i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
1104
1105         if (!(msg->flags & I2C_M_RD))
1106                 tegra_i2c_fill_tx_fifo(i2c_dev);
1107
1108         if (i2c_dev->is_dvc)
1109                 dvc_i2c_unmask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
1110
1111         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST
1112                                         | I2C_INT_TX_FIFO_OVERFLOW;
1113         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
1114                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1115
1116         if (i2c_dev->chipdata->has_xfer_complete_interrupt)
1117                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
1118
1119         if (msg->flags & I2C_M_RD)
1120                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1121         else if (i2c_dev->msg_buf_remaining)
1122                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1123
1124         if (next_msg != NULL) {
1125                 tegra_i2c_send_next_read_msg_pkt_header(i2c_dev, next_msg,
1126                                                         next_msg_end_state);
1127                 tegra_i2c_copy_next_to_current(i2c_dev);
1128                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1129                 i2c_dev->use_single_xfer_complete = false;
1130         }
1131
1132         if (!(i2c_dev->use_single_xfer_complete &&
1133                         i2c_dev->chipdata->has_xfer_complete_interrupt))
1134                 int_mask |= I2C_INT_ALL_PACKETS_XFER_COMPLETE;
1135
1136         if (!i2c_dev->is_interruptable_xfer)
1137                 spin_unlock_irqrestore(&i2c_dev->fifo_lock, flags);
1138
1139         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1140
1141         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1142                 i2c_readl(i2c_dev, I2C_INT_MASK));
1143
1144         ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
1145                                         TEGRA_I2C_TIMEOUT);
1146         if (ret == 0) {
1147                 dev_err(i2c_dev->dev, "--- register dump for debugging ----\n");
1148                 dev_err(i2c_dev->dev, "I2C_CNFG - 0x%x\n",
1149                         i2c_readl(i2c_dev, I2C_CNFG));
1150                 dev_err(i2c_dev->dev, "I2C_PACKET_TRANSFER_STATUS - 0x%x\n",
1151                         i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
1152                 dev_err(i2c_dev->dev, "I2C_FIFO_CONTROL - 0x%x\n",
1153                         i2c_readl(i2c_dev, I2C_FIFO_CONTROL));
1154                 dev_err(i2c_dev->dev, "I2C_FIFO_STATUS - 0x%x\n",
1155                         i2c_readl(i2c_dev, I2C_FIFO_STATUS));
1156                 dev_err(i2c_dev->dev, "I2C_INT_MASK - 0x%x\n",
1157                         i2c_readl(i2c_dev, I2C_INT_MASK));
1158                 dev_err(i2c_dev->dev, "I2C_INT_STATUS - 0x%x\n",
1159                         i2c_readl(i2c_dev, I2C_INT_STATUS));
1160
1161                 dev_err(i2c_dev->dev, "msg->len - %d\n", msg->len);
1162                 dev_err(i2c_dev->dev, "is_msg_write - %d\n",
1163                         !(msg->flags & I2C_M_RD));
1164                 if (next_msg != NULL) {
1165                         dev_err(i2c_dev->dev, "next_msg->len - %d\n",
1166                                 next_msg->len);
1167                         dev_err(i2c_dev->dev, "is_next_msg_write - %d\n",
1168                                 !(next_msg->flags & I2C_M_RD));
1169                 }
1170
1171                 dev_err(i2c_dev->dev, "buf_remaining - %zd\n",
1172                         i2c_dev->msg_buf_remaining);
1173         }
1174
1175         tegra_i2c_mask_irq(i2c_dev, int_mask);
1176
1177         if (i2c_dev->is_dvc)
1178                 dvc_i2c_mask_irq(i2c_dev, DVC_CTRL_REG3_I2C_DONE_INTR_EN);
1179
1180         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
1181         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
1182                 i2c_writel(i2c_dev, cnfg & (~I2C_CNFG_PACKET_MODE_EN),
1183                                                                 I2C_CNFG);
1184         else
1185                 dev_err(i2c_dev->dev, "i2c_cnfg PACKET_MODE_EN not set\n");
1186
1187         if (i2c_dev->chipdata->has_config_load_reg) {
1188                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
1189                                         I2C_CONFIG_LOAD);
1190                 timeout = jiffies + msecs_to_jiffies(1000);
1191                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
1192                         if (time_after(jiffies, timeout)) {
1193                                 dev_warn(i2c_dev->dev,
1194                                         "timeout config_load");
1195                                 return -ETIMEDOUT;
1196                         }
1197                         udelay(2);
1198                 }
1199         }
1200
1201         if (ret == 0) {
1202                 dev_err(i2c_dev->dev,
1203                         "i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
1204                         msg->addr, msg->buf[0]);
1205
1206                 ret = tegra_i2c_init(i2c_dev);
1207                 if (!ret)
1208                         ret = -ETIMEDOUT;
1209                 else
1210                         WARN_ON(1);
1211                 return ret;
1212         }
1213
1214         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
1215                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
1216
1217         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1218                 return 0;
1219
1220         /* Prints errors */
1221         if (i2c_dev->msg_err & I2C_ERR_UNKNOWN_INTERRUPT)
1222                 dev_warn(i2c_dev->dev, "unknown interrupt Add 0x%02x\n",
1223                                 i2c_dev->msg_add);
1224         if (i2c_dev->msg_err & I2C_ERR_NO_ACK)
1225                 dev_warn(i2c_dev->dev, "no acknowledge from address 0x%x\n",
1226                                 i2c_dev->msg_add);
1227         if (i2c_dev->msg_err & I2C_ERR_ARBITRATION_LOST)
1228                 dev_warn(i2c_dev->dev, "arb lost in communicate to add 0x%x\n",
1229                                 i2c_dev->msg_add);
1230         if (i2c_dev->msg_err & I2C_INT_TX_FIFO_OVERFLOW)
1231                 dev_warn(i2c_dev->dev, "Tx fifo overflow to add 0x%x\n",
1232                                 i2c_dev->msg_add);
1233         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
1234                 dev_warn(i2c_dev->dev, "unexpected status to add 0x%x\n",
1235                                 i2c_dev->msg_add);
1236
1237         if ((i2c_dev->chipdata->timeout_irq_occurs_before_bus_inactive) &&
1238                 (i2c_dev->msg_err == I2C_ERR_NO_ACK)) {
1239                 /*
1240                 * In NACK error condition resetting of I2C controller happens
1241                 * before STOP condition is properly completed by I2C controller,
1242                 * so wait for 2 clock cycle to complete STOP condition.
1243                 */
1244                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
1245         }
1246
1247         /*
1248          * NACK interrupt is generated before the I2C controller generates the
1249          * STOP condition on the bus. So wait for 2 clock periods before resetting
1250          * the controller so that STOP condition has been delivered properly.
1251          */
1252         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
1253                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
1254
1255         ret = tegra_i2c_init(i2c_dev);
1256         if (ret) {
1257                 WARN_ON(1);
1258                 return ret;
1259         }
1260
1261         /* Arbitration Lost occurs, Start recovery */
1262         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1263                 if (i2c_dev->chipdata->has_hw_arb_support) {
1264                         INIT_COMPLETION(i2c_dev->msg_complete);
1265                         i2c_writel(i2c_dev, I2C_BC_ENABLE
1266                                         | I2C_BC_SCLK_THRESHOLD
1267                                         | I2C_BC_STOP_COND
1268                                         | I2C_BC_TERMINATE
1269                                         , I2C_BUS_CLEAR_CNFG);
1270
1271                         if (i2c_dev->chipdata->has_config_load_reg) {
1272                                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD,
1273                                                         I2C_CONFIG_LOAD);
1274                                 timeout = jiffies + msecs_to_jiffies(1000);
1275                                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
1276                                         if (time_after(jiffies, timeout)) {
1277                                                 dev_warn(i2c_dev->dev,
1278                                                         "timeout config_load");
1279                                                 return -ETIMEDOUT;
1280                                         }
1281                                         msleep(1);
1282                                 }
1283                         }
1284
1285                         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLEAR_DONE);
1286
1287                         wait_for_completion_timeout(&i2c_dev->msg_complete,
1288                                 TEGRA_I2C_TIMEOUT);
1289
1290                         if (!(i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS) & I2C_BC_STATUS))
1291                                 dev_warn(i2c_dev->dev, "Un-recovered Arbitration lost\n");
1292                 } else {
1293                         i2c_algo_busclear_gpio(i2c_dev->dev,
1294                                 i2c_dev->scl_gpio, GPIOF_OPEN_DRAIN,
1295                                 i2c_dev->sda_gpio,GPIOF_OPEN_DRAIN,
1296                                 MAX_BUSCLEAR_CLOCK, 100000);
1297                 }
1298                 return -EAGAIN;
1299         }
1300
1301         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
1302                 return -EREMOTEIO;
1303
1304         if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
1305                 return -EAGAIN;
1306
1307         return -EIO;
1308 }
1309
1310 static int tegra_i2c_split_i2c_msg_xfer(struct tegra_i2c_dev *i2c_dev,
1311                 struct i2c_msg *msg, enum msg_end_type end_type,
1312                 enum msg_end_type next_msg_end_type)
1313 {
1314         int size, len, ret;
1315         struct i2c_msg temp_msg;
1316         u8 *buf = msg->buf;
1317         enum msg_end_type temp_end_type;
1318
1319         size = msg->len;
1320         temp_msg.flags = msg->flags;
1321         temp_msg.addr = msg->addr;
1322         temp_end_type = end_type;
1323         do {
1324                 temp_msg.buf = buf;
1325                 len = min(size, I2C_MAX_TRANSFER_LEN);
1326                 temp_msg.len = len;
1327                 size -= len;
1328                 if ((len == I2C_MAX_TRANSFER_LEN) && size)
1329                         end_type = MSG_END_CONTINUE;
1330                 else
1331                         end_type = temp_end_type;
1332                 ret = tegra_i2c_xfer_msg(i2c_dev, &temp_msg, end_type,
1333                                 NULL, next_msg_end_type);
1334                 if (ret)
1335                         return ret;
1336                 buf += len;
1337         } while (size != 0);
1338
1339         return ret;
1340 }
1341
1342 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1343         int num)
1344 {
1345         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1346         int i;
1347         int ret = 0;
1348         BUG_ON(!rt_mutex_is_locked(&(adap->bus_lock)));
1349         if (i2c_dev->is_suspended)
1350                 return -EBUSY;
1351
1352         if ((i2c_dev->is_shutdown || adap->atomic_xfer_only)
1353                 && i2c_dev->bit_banging_xfer_after_shutdown)
1354                 return tegra_i2c_gpio_xfer(adap, msgs, num);
1355
1356         if (adap->atomic_xfer_only)
1357                 return -EBUSY;
1358
1359         if (adap->bus_clk_rate != i2c_dev->bus_clk_rate) {
1360                 i2c_dev->bus_clk_rate = adap->bus_clk_rate;
1361                 ret = tegra_i2c_set_clk_rate(i2c_dev);
1362                 if (ret < 0)
1363                         return ret;
1364         }
1365
1366         i2c_dev->msgs = msgs;
1367         i2c_dev->msgs_num = num;
1368
1369         pm_runtime_get_sync(&adap->dev);
1370         ret = tegra_i2c_clock_enable(i2c_dev);
1371         if (ret < 0) {
1372                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
1373                 pm_runtime_put(&adap->dev);
1374                 return ret;
1375         }
1376
1377         for (i = 0; i < num; i++) {
1378                 enum msg_end_type end_type = MSG_END_STOP;
1379                 enum msg_end_type next_msg_end_type = MSG_END_STOP;
1380
1381                 if (i < (num - 1)) {
1382                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1383                                 end_type = MSG_END_CONTINUE;
1384                         else
1385                                 end_type = MSG_END_REPEAT_START;
1386                         if (i < num - 2) {
1387                                 if (msgs[i + 2].flags & I2C_M_NOSTART)
1388                                         next_msg_end_type = MSG_END_CONTINUE;
1389                                 else
1390                                         next_msg_end_type = MSG_END_REPEAT_START;
1391                         }
1392                         if ((!(msgs[i].flags & I2C_M_RD)) && (msgs[i].len <= 8)
1393                                 && (msgs[i+1].flags & I2C_M_RD)
1394                                 && (msgs[i+1].len <= I2C_MAX_TRANSFER_LEN)
1395                                 && (next_msg_end_type != MSG_END_CONTINUE)
1396                                 && (end_type == MSG_END_REPEAT_START)) {
1397                                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type, &msgs[i+1], next_msg_end_type);
1398                                 if (ret)
1399                                         break;
1400                                 i++;
1401                         } else {
1402                                 if (msgs[i].len > I2C_MAX_TRANSFER_LEN) {
1403                                         ret = tegra_i2c_split_i2c_msg_xfer(i2c_dev, &msgs[i],
1404                                                         end_type, next_msg_end_type);
1405                                         if (ret)
1406                                                 break;
1407                                 } else {
1408                                         ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type,
1409                                                         NULL, next_msg_end_type);
1410                                         if (ret)
1411                                                 break;
1412                                 }
1413                         }
1414                 } else {
1415                         if (msgs[i].len > I2C_MAX_TRANSFER_LEN) {
1416                                 ret = tegra_i2c_split_i2c_msg_xfer(i2c_dev,
1417                                                 &msgs[i], end_type,
1418                                                 next_msg_end_type);
1419                                 if (ret)
1420                                         break;
1421                         } else {
1422                                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type, NULL, next_msg_end_type);
1423                                 if (ret)
1424                                         break;
1425                         }
1426                 }
1427         }
1428
1429         tegra_i2c_clock_disable(i2c_dev);
1430         pm_runtime_put(&adap->dev);
1431
1432         i2c_dev->msgs = NULL;
1433         i2c_dev->msgs_num = 0;
1434
1435         return ret ?: i;
1436 }
1437
1438 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1439 {
1440         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1441         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
1442                                 I2C_FUNC_PROTOCOL_MANGLING;
1443
1444         if (i2c_dev->chipdata->has_continue_xfer_support)
1445                 ret |= I2C_FUNC_NOSTART;
1446         return ret;
1447 }
1448
1449 static const struct i2c_algorithm tegra_i2c_algo = {
1450         .master_xfer    = tegra_i2c_xfer,
1451         .functionality  = tegra_i2c_func,
1452 };
1453
1454 static int tegra_i2c_pm_notifier(struct notifier_block *nb,
1455         unsigned long event, void *data);
1456
1457 static struct tegra_i2c_platform_data *parse_i2c_tegra_dt(
1458         struct platform_device *pdev)
1459 {
1460         struct tegra_i2c_platform_data *pdata;
1461         struct device_node *np = pdev->dev.of_node;
1462         u32 prop;
1463
1464         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1465         if (!pdata)
1466                 return ERR_PTR(-ENOMEM);
1467
1468         if (!of_property_read_u32(np, "clock-frequency", &prop))
1469                 pdata->bus_clk_rate = prop;
1470
1471         pdata->is_clkon_always = of_property_read_bool(np,
1472                                         "nvidia,clock-always-on");
1473
1474         if (!of_property_read_u32(np, "nvidia,hs-master-code", &prop)) {
1475                 pdata->hs_master_code = prop;
1476                 pdata->is_high_speed_enable = true;
1477         }
1478
1479         pdata->is_interruptable_xfer = of_property_read_bool(np,
1480                                         "nvidia,interruptable-transfer");
1481         pdata->needs_cl_dvfs_clock = of_property_read_bool(np,
1482                                         "nvidia,require-cldvfs-clock");
1483
1484         pdata->bit_banging_xfer_after_shutdown = of_property_read_bool(np,
1485                                         "nvidia,bit-banging-xfer-after-shutdown");
1486
1487         pdata->scl_gpio = of_get_named_gpio(np, "scl-gpio", 0);
1488         pdata->sda_gpio = of_get_named_gpio(np, "sda-gpio", 0);
1489         pdata->is_dvc = of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc");
1490
1491         pdata->is_multimaster_mode = of_property_read_bool(np,
1492                         "nvidia,multimaster-mode");
1493
1494         if (pdata->is_multimaster_mode)
1495                 pdata->is_clkon_always = true;
1496
1497         /* Default configuration for device tree initiated driver */
1498         pdata->slave_addr = 0xFC;
1499         return pdata;
1500 }
1501
1502 static struct tegra_i2c_chipdata tegra20_i2c_chipdata = {
1503         .timeout_irq_occurs_before_bus_inactive = true,
1504         .has_xfer_complete_interrupt = false,
1505         .has_continue_xfer_support = false,
1506         .has_hw_arb_support = false,
1507         .has_fast_clock = true,
1508         .has_clk_divisor_std_fast_mode = false,
1509         .clk_divisor_std_fast_mode = 0,
1510         .clk_divisor_hs_mode = 3,
1511         .clk_multiplier_hs_mode = 12,
1512         .has_config_load_reg = false,
1513         .has_multi_master_en_bit = false,
1514         .has_clk_override_reg = false,
1515 };
1516
1517 static struct tegra_i2c_chipdata tegra30_i2c_chipdata = {
1518         .timeout_irq_occurs_before_bus_inactive = true,
1519         .has_xfer_complete_interrupt = false,
1520         .has_continue_xfer_support = true,
1521         .has_hw_arb_support = false,
1522         .has_fast_clock = true,
1523         .has_clk_divisor_std_fast_mode = false,
1524         .clk_divisor_std_fast_mode = 0,
1525         .clk_divisor_hs_mode = 3,
1526         .clk_multiplier_hs_mode = 12,
1527         .has_config_load_reg = false,
1528         .has_multi_master_en_bit = false,
1529         .has_clk_override_reg = false,
1530 };
1531
1532 static struct tegra_i2c_chipdata tegra114_i2c_chipdata = {
1533         .timeout_irq_occurs_before_bus_inactive = false,
1534         .has_xfer_complete_interrupt = true,
1535         .has_continue_xfer_support = true,
1536         .has_hw_arb_support = true,
1537         .has_fast_clock = false,
1538         .has_clk_divisor_std_fast_mode = true,
1539         .clk_divisor_std_fast_mode = 0x19,
1540         .clk_divisor_fast_plus_mode = 0x10,
1541         .clk_divisor_hs_mode = 1,
1542         .clk_multiplier_hs_mode = 3,
1543         .has_config_load_reg = false,
1544         .has_multi_master_en_bit = false,
1545         .has_clk_override_reg = false,
1546 };
1547
1548 static struct tegra_i2c_chipdata tegra148_i2c_chipdata = {
1549         .timeout_irq_occurs_before_bus_inactive = false,
1550         .has_xfer_complete_interrupt = true,
1551         .has_continue_xfer_support = true,
1552         .has_hw_arb_support = true,
1553         .has_fast_clock = false,
1554         .has_clk_divisor_std_fast_mode = true,
1555         .clk_divisor_std_fast_mode = 0x19,
1556         .clk_divisor_fast_plus_mode = 0x19,
1557         .clk_divisor_hs_mode = 2,
1558         .clk_multiplier_hs_mode = 13,
1559         .has_config_load_reg = true,
1560         .has_multi_master_en_bit = false,
1561         .has_clk_override_reg = true,
1562 };
1563
1564 static struct tegra_i2c_chipdata tegra124_i2c_chipdata = {
1565         .timeout_irq_occurs_before_bus_inactive = false,
1566         .has_xfer_complete_interrupt = true,
1567         .has_continue_xfer_support = true,
1568         .has_hw_arb_support = true,
1569         .has_fast_clock = false,
1570         .has_clk_divisor_std_fast_mode = true,
1571         .clk_divisor_std_fast_mode = 0x19,
1572         .clk_divisor_fast_plus_mode = 0x10,
1573         .clk_divisor_hs_mode = 2,
1574         .clk_multiplier_hs_mode = 13,
1575         .has_config_load_reg = true,
1576         .has_multi_master_en_bit = false,
1577         .has_clk_override_reg = true,
1578 };
1579
1580 static struct tegra_i2c_chipdata tegra210_i2c_chipdata = {
1581         .timeout_irq_occurs_before_bus_inactive = false,
1582         .has_xfer_complete_interrupt = true,
1583         .has_continue_xfer_support = true,
1584         .has_hw_arb_support = true,
1585         .has_fast_clock = false,
1586         .has_clk_divisor_std_fast_mode = true,
1587         .clk_divisor_std_fast_mode = 0x19,
1588         .clk_divisor_fast_plus_mode = 0x10,
1589         .clk_divisor_hs_mode = 2,
1590         .clk_multiplier_hs_mode = 13,
1591         .has_config_load_reg = true,
1592         .has_multi_master_en_bit = true,
1593         .has_clk_override_reg = true,
1594 };
1595
1596 /* Match table for of_platform binding */
1597 static const struct of_device_id tegra_i2c_of_match[] = {
1598         { .compatible = "nvidia,tegra210-i2c",
1599                                         .data = &tegra210_i2c_chipdata, },
1600         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_chipdata, },
1601         { .compatible = "nvidia,tegra148-i2c", .data = &tegra148_i2c_chipdata, },
1602         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_chipdata, },
1603         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_chipdata, },
1604         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_chipdata, },
1605         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_chipdata, },
1606         {},
1607 };
1608 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1609
1610 static struct platform_device_id tegra_i2c_devtype[] = {
1611         {
1612                 .name = "tegra-i2c",
1613                 .driver_data = (unsigned long)&tegra30_i2c_chipdata,
1614         },
1615         {
1616                 .name = "tegra20-i2c",
1617                 .driver_data = (unsigned long)&tegra20_i2c_chipdata,
1618         },
1619         {
1620                 .name = "tegra30-i2c",
1621                 .driver_data = (unsigned long)&tegra30_i2c_chipdata,
1622         },
1623         {
1624                 .name = "tegra11-i2c",
1625                 .driver_data = (unsigned long)&tegra114_i2c_chipdata,
1626         },
1627         {
1628                 .name = "tegra14-i2c",
1629                 .driver_data = (unsigned long)&tegra148_i2c_chipdata,
1630         },
1631         {
1632                 .name = "tegra12-i2c",
1633                 .driver_data = (unsigned long)&tegra124_i2c_chipdata,
1634         },
1635         {
1636                 .name = "tegra21-i2c",
1637                 .driver_data = (unsigned long)&tegra210_i2c_chipdata,
1638         },
1639 };
1640
1641 static int tegra_i2c_probe(struct platform_device *pdev)
1642 {
1643         struct tegra_i2c_dev *i2c_dev;
1644         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
1645         struct resource *res;
1646         struct clk *div_clk;
1647         struct clk *fast_clk = NULL;
1648         struct clk *dvfs_ref_clk = NULL;
1649         struct clk *dvfs_soc_clk = NULL;
1650         void __iomem *base;
1651         int irq;
1652         int ret = 0;
1653         const struct tegra_i2c_chipdata *chip_data = NULL;
1654         const struct of_device_id *match;
1655         int bus_num = -1;
1656         struct pinctrl *pin;
1657         struct pinctrl_state *s;
1658         char prod_name[15];
1659
1660         if (pdev->dev.of_node) {
1661                 match = of_match_device(of_match_ptr(tegra_i2c_of_match), &pdev->dev);
1662                 if (!match) {
1663                         dev_err(&pdev->dev, "Device Not matching\n");
1664                         return -ENODEV;
1665                 }
1666                 chip_data = match->data;
1667                 if (!pdata)
1668                         pdata = parse_i2c_tegra_dt(pdev);
1669         } else {
1670                 chip_data = (struct tegra_i2c_chipdata *)pdev->id_entry->driver_data;
1671                 bus_num = pdev->id;
1672         }
1673
1674         if (IS_ERR(pdata) || !pdata || !chip_data) {
1675                 dev_err(&pdev->dev, "no platform/chip data?\n");
1676                 return IS_ERR(pdata) ? PTR_ERR(pdata) : -ENODEV;
1677         }
1678
1679         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680         if (!res) {
1681                 dev_err(&pdev->dev, "no mem resource\n");
1682                 return -EINVAL;
1683         }
1684
1685         base = devm_ioremap_resource(&pdev->dev, res);
1686         if (IS_ERR(base))
1687                 return PTR_ERR(base);
1688
1689         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1690         if (!res) {
1691                 dev_err(&pdev->dev, "no irq resource\n");
1692                 return -EINVAL;
1693         }
1694         irq = res->start;
1695
1696         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1697         if (!i2c_dev) {
1698                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
1699                 return -ENOMEM;
1700         }
1701
1702         i2c_dev->chipdata = chip_data;
1703         i2c_dev->needs_cl_dvfs_clock = pdata->needs_cl_dvfs_clock;
1704         i2c_dev->is_interruptable_xfer = pdata->is_interruptable_xfer;
1705
1706         div_clk = devm_clk_get(&pdev->dev, "div-clk");
1707         if (IS_ERR(div_clk)) {
1708                 dev_err(&pdev->dev, "missing controller clock");
1709                 return PTR_ERR(div_clk);
1710         }
1711
1712         if (i2c_dev->chipdata->has_fast_clock) {
1713                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1714                 if (IS_ERR(fast_clk)) {
1715                         dev_err(&pdev->dev, "missing bus clock");
1716                         return PTR_ERR(fast_clk);
1717                 }
1718         }
1719
1720         if (i2c_dev->needs_cl_dvfs_clock) {
1721                 dvfs_ref_clk = devm_clk_get(&pdev->dev, "cl_dvfs_ref");
1722                 if (IS_ERR(dvfs_ref_clk)) {
1723                         dev_err(&pdev->dev, "missing cl_dvfs_ref clock");
1724                         return PTR_ERR(dvfs_ref_clk);
1725                 }
1726                 i2c_dev->dvfs_ref_clk = dvfs_ref_clk;
1727                 dvfs_soc_clk = devm_clk_get(&pdev->dev, "cl_dvfs_soc");
1728                 if (IS_ERR(dvfs_soc_clk)) {
1729                         dev_err(&pdev->dev, "missing cl_dvfs_soc clock");
1730                         return PTR_ERR(dvfs_soc_clk);
1731                 }
1732                 i2c_dev->dvfs_soc_clk = dvfs_soc_clk;
1733         }
1734
1735         if (pdata->is_high_speed_enable) {
1736                 pin = devm_pinctrl_get(&pdev->dev);
1737                 if (IS_ERR(pin)) {
1738                         dev_warn(&pdev->dev, "Missing pinctrl device\n");
1739                         goto skip_pinctrl;
1740                 }
1741
1742                 s = pinctrl_lookup_state(pin, "hs_mode");
1743                 if (IS_ERR(s)) {
1744                         dev_warn(&pdev->dev, "Missing hs_mode state\n");
1745                         goto skip_pinctrl;
1746                 }
1747
1748                 ret = pinctrl_select_state(pin, s);
1749                 if (ret < 0)
1750                         dev_err(&pdev->dev, "setting state failed\n");
1751         }
1752
1753 skip_pinctrl:
1754
1755         i2c_dev->base = base;
1756         i2c_dev->div_clk = div_clk;
1757         if (i2c_dev->chipdata->has_fast_clock)
1758                 i2c_dev->fast_clk = fast_clk;
1759         i2c_dev->irq = irq;
1760         i2c_dev->dev = &pdev->dev;
1761         i2c_dev->is_clkon_always = pdata->is_clkon_always;
1762         i2c_dev->is_multimaster_mode = pdata->is_multimaster_mode;
1763         i2c_dev->bus_clk_rate = pdata->bus_clk_rate ? pdata->bus_clk_rate: 100000;
1764         i2c_dev->is_high_speed_enable = pdata->is_high_speed_enable;
1765         i2c_dev->clk_divisor_non_hs_mode =
1766                         i2c_dev->chipdata->clk_divisor_std_fast_mode;
1767         if (i2c_dev->bus_clk_rate == 1000000)
1768                 i2c_dev->clk_divisor_non_hs_mode =
1769                         i2c_dev->chipdata->clk_divisor_fast_plus_mode;
1770         i2c_dev->msgs = NULL;
1771         i2c_dev->msgs_num = 0;
1772         i2c_dev->is_dvc = pdata->is_dvc;
1773         i2c_dev->slave_addr = pdata->slave_addr;
1774         i2c_dev->hs_master_code = pdata->hs_master_code;
1775         i2c_dev->bit_banging_xfer_after_shutdown =
1776                         pdata->bit_banging_xfer_after_shutdown;
1777         init_completion(&i2c_dev->msg_complete);
1778
1779         spin_lock_init(&i2c_dev->fifo_lock);
1780
1781         spin_lock_init(&i2c_dev->mem_lock);
1782
1783         if (pdev->dev.of_node)
1784                 i2c_dev->prod_list = tegra_prod_init(pdev->dev.of_node);
1785         if (IS_ERR(i2c_dev->prod_list))
1786                 i2c_dev->prod_list = NULL;
1787
1788         platform_set_drvdata(pdev, i2c_dev);
1789
1790         if (i2c_dev->is_clkon_always)
1791                 tegra_i2c_clock_enable(i2c_dev);
1792
1793         ret = tegra_i2c_init(i2c_dev);
1794         if (ret) {
1795                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
1796                 goto err;
1797         }
1798
1799         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1800                         tegra_i2c_isr, IRQF_NO_SUSPEND,
1801                         dev_name(&pdev->dev), i2c_dev);
1802         if (ret) {
1803                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1804                 goto err;
1805         }
1806
1807         pm_runtime_enable(&pdev->dev);
1808
1809         i2c_dev->scl_gpio = pdata->scl_gpio;
1810         i2c_dev->sda_gpio = pdata->sda_gpio;
1811         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1812         i2c_dev->adapter.owner = THIS_MODULE;
1813         i2c_dev->adapter.class = I2C_CLASS_HWMON;
1814         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
1815                 sizeof(i2c_dev->adapter.name));
1816         i2c_dev->adapter.bus_clk_rate = i2c_dev->bus_clk_rate;
1817         i2c_dev->adapter.algo = &tegra_i2c_algo;
1818         i2c_dev->adapter.dev.parent = &pdev->dev;
1819         i2c_dev->adapter.nr = bus_num;
1820         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1821
1822         if (pdata->retries)
1823                 i2c_dev->adapter.retries = pdata->retries;
1824         else
1825                 i2c_dev->adapter.retries = TEGRA_I2C_RETRIES;
1826
1827         if (pdata->timeout)
1828                 i2c_dev->adapter.timeout = pdata->timeout;
1829
1830         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1831         if (ret) {
1832                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
1833                 goto err;
1834         }
1835         i2c_dev->cont_id = i2c_dev->adapter.nr & PACKET_HEADER0_CONT_ID_MASK;
1836         if (pdata->is_high_speed_enable) {
1837                 sprintf(prod_name, "i2c%d_hs_prod", i2c_dev->cont_id);
1838                 ret = tegra_pinctrl_config_prod(&pdev->dev, prod_name);
1839                 if (ret < 0)
1840                         dev_warn(&pdev->dev, "Failed to set %s setting\n",
1841                                         prod_name);
1842         }
1843
1844         i2c_dev->pm_nb.notifier_call = tegra_i2c_pm_notifier;
1845
1846         tegra_register_pm_notifier(&i2c_dev->pm_nb);
1847
1848         of_i2c_register_devices(&i2c_dev->adapter);
1849         pm_runtime_enable(&i2c_dev->adapter.dev);
1850         tegra_i2c_gpio_init(i2c_dev);
1851
1852         return 0;
1853 err:
1854         tegra_prod_release(&i2c_dev->prod_list);
1855         return ret;
1856 }
1857
1858 static int tegra_i2c_remove(struct platform_device *pdev)
1859 {
1860         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1861
1862         tegra_unregister_pm_notifier(&i2c_dev->pm_nb);
1863         i2c_del_adapter(&i2c_dev->adapter);
1864         pm_runtime_disable(&i2c_dev->adapter.dev);
1865
1866         if (i2c_dev->is_clkon_always)
1867                 tegra_i2c_clock_disable(i2c_dev);
1868
1869         pm_runtime_disable(&pdev->dev);
1870         tegra_prod_release(&i2c_dev->prod_list);
1871         return 0;
1872 }
1873
1874 static void tegra_i2c_shutdown(struct platform_device *pdev)
1875 {
1876         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1877
1878         dev_info(i2c_dev->dev, "Shutting down\n");
1879         i2c_shutdown_adapter(&i2c_dev->adapter);
1880         i2c_dev->is_shutdown = true;
1881 }
1882
1883 #ifdef CONFIG_PM_SLEEP
1884 static int __tegra_i2c_suspend_noirq_late(struct tegra_i2c_dev *i2c_dev)
1885 {
1886         i2c_dev->is_suspended = true;
1887         if (i2c_dev->is_clkon_always)
1888                 tegra_i2c_clock_disable(i2c_dev);
1889
1890         return 0;
1891 }
1892
1893 static int tegra_i2c_suspend_noirq_late(struct device *dev)
1894 {
1895         struct platform_device *pdev = to_platform_device(dev);
1896         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1897
1898         i2c_lock_adapter(&i2c_dev->adapter);
1899
1900         __tegra_i2c_suspend_noirq_late(i2c_dev);
1901
1902         i2c_unlock_adapter(&i2c_dev->adapter);
1903
1904         return 0;
1905 }
1906
1907 static int __tegra_i2c_resume_noirq_early(struct tegra_i2c_dev *i2c_dev)
1908 {
1909         int ret;
1910
1911         if (i2c_dev->is_clkon_always)
1912                 tegra_i2c_clock_enable(i2c_dev);
1913
1914         ret = tegra_i2c_init(i2c_dev);
1915         if (ret)
1916                 return ret;
1917
1918         i2c_dev->is_suspended = false;
1919
1920         return 0;
1921 }
1922
1923 static int tegra_i2c_resume_noirq_early(struct device *dev)
1924 {
1925         struct platform_device *pdev = to_platform_device(dev);
1926         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1927
1928         i2c_lock_adapter(&i2c_dev->adapter);
1929
1930         __tegra_i2c_resume_noirq_early(i2c_dev);
1931
1932         i2c_unlock_adapter(&i2c_dev->adapter);
1933
1934         return 0;
1935 }
1936
1937 static int tegra_i2c_pm_notifier(struct notifier_block *nb,
1938                 unsigned long event, void *data)
1939 {
1940         struct tegra_i2c_dev *i2c_dev = container_of(nb, struct tegra_i2c_dev, pm_nb);
1941
1942         if (event == TEGRA_PM_SUSPEND)
1943                 __tegra_i2c_suspend_noirq_late(i2c_dev);
1944         else if (event == TEGRA_PM_RESUME)
1945                 __tegra_i2c_resume_noirq_early(i2c_dev);
1946
1947         return NOTIFY_OK;
1948 }
1949
1950 static const struct dev_pm_ops tegra_i2c_pm = {
1951         .suspend_noirq_late = tegra_i2c_suspend_noirq_late,
1952         .resume_noirq_early = tegra_i2c_resume_noirq_early,
1953 };
1954 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1955 #else
1956 #define TEGRA_I2C_PM    NULL
1957 static int tegra_i2c_pm_notifier(struct notifier_block *nb,
1958                 unsigned long event, void *data)
1959 {
1960         return NOTIFY_OK;
1961 }
1962 #endif
1963
1964 static struct platform_driver tegra_i2c_driver = {
1965         .probe   = tegra_i2c_probe,
1966         .remove  = tegra_i2c_remove,
1967         .late_shutdown = tegra_i2c_shutdown,
1968         .id_table = tegra_i2c_devtype,
1969         .driver  = {
1970                 .name  = "tegra-i2c",
1971                 .owner = THIS_MODULE,
1972                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
1973                 .pm    = TEGRA_I2C_PM,
1974         },
1975 };
1976
1977 static int __init tegra_i2c_init_driver(void)
1978 {
1979         return platform_driver_register(&tegra_i2c_driver);
1980 }
1981
1982 static void __exit tegra_i2c_exit_driver(void)
1983 {
1984         platform_driver_unregister(&tegra_i2c_driver);
1985 }
1986
1987 subsys_initcall(tegra_i2c_init_driver);
1988 module_exit(tegra_i2c_exit_driver);
1989
1990 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1991 MODULE_AUTHOR("Colin Cross");
1992 MODULE_LICENSE("GPL v2");