i2c: tegra: override slcg for Master core logic

i2c: tegra: override slcg for Master core logic

- override(disable) 2nd-level clock for I2C master
core logic i.e keeping 2nd-level clock always ON
when bus is operating in multi-master mode.

Bug 200146630

Change-Id: I04840c2a0453ecbf5c10a9ea0e0f3d0523c5071a
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/842347
(cherry picked from commit 115380a0fff228cb606e135e703d87c297070835)
Reviewed-on: http://git-master/r/1190655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>