drivers/usb/host/ehci-tegra.c

   1 /*
   2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2009 - 2011 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/platform_data/tegra_usb.h>
  23 #include <linux/irq.h>
  24 #include <linux/usb/otg.h>
  25 #include <linux/gpio.h>
  26 #include <linux/of.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include <linux/usb/tegra_usb_phy.h>
  31
  32 #define TEGRA_USB_BASE                  0xC5000000
  33 #define TEGRA_USB2_BASE                 0xC5004000
  34 #define TEGRA_USB3_BASE                 0xC5008000
  35
  36 #define TEGRA_USB_PORTSC_PHCD           (1 << 23)
  37
  38 #define TEGRA_USB_SUSP_CTRL_OFFSET      0x400
  39 #define TEGRA_USB_SUSP_CLR                      (1 << 5)
  40 #define TEGRA_USB_PHY_CLK_VALID                 (1 << 7)
  41 #define TEGRA_USB_SRT                           (1 << 25)
  42 #define TEGRA_USB_PHY_CLK_VALID_INT_ENB         (1 << 9)
  43 #define TEGRA_USB_PHY_CLK_VALID_INT_STS         (1 << 8)
  44
  45 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  46 #define TEGRA_USB_PORTSC1_OFFSET        0x184
  47 #else
  48 #define TEGRA_USB_PORTSC1_OFFSET        0x174
  49 #endif
  50 #define TEGRA_USB_PORTSC1_WKCN                  (1 << 20)
  51
  52 #define TEGRA_LVL2_CLK_GATE_OVRB        0xfc
  53 #define TEGRA_USB2_CLK_OVR_ON                   (1 << 10)
  54
  55 #define TEGRA_USB_DMA_ALIGN 32
  56
  57 #define STS_SRI (1<<7)  /*      SOF Recieved    */
  58
  59 #define TEGRA_HSIC_CONNECTION_MAX_RETRIES 5
  60 #define HOSTPC_REG_OFFSET               0x1b4
  61
  62 #define HOSTPC1_DEVLC_STS               (1 << 28)
  63 #define HOSTPC1_DEVLC_PTS(x)            (((x) & 0x7) << 29)
  64
  65 struct tegra_ehci_hcd {
  66         struct ehci_hcd *ehci;
  67         struct tegra_usb_phy *phy;
  68         struct clk *clk;
  69         struct clk *emc_clk;
  70         struct clk *sclk_clk;
  71         struct usb_phy *transceiver;
  72         int host_resumed;
  73         int port_resuming;
  74         int default_enable;
  75         struct delayed_work work;
  76         enum tegra_usb_phy_port_speed port_speed;
  77         struct work_struct clk_timer_work;
  78         struct timer_list clk_timer;
  79         bool clock_enabled;
  80         bool timer_event;
  81         int hsic_connect_retries;
  82         unsigned int irq;
  83 };
  84
  85 static void tegra_ehci_power_up(struct usb_hcd *hcd)
  86 {
  87         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  88
  89         if (!tegra->default_enable)
  90                 clk_enable(tegra->clk);
  91         usb_phy_set_suspend(&tegra->phy->u_phy, 0);
  92         tegra->host_resumed = 1;
  93 }
  94
  95 static void tegra_ehci_power_down(struct usb_hcd *hcd)
  96 {
  97         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  98
  99         tegra->host_resumed = 0;
 100         usb_phy_set_suspend(&tegra->phy->u_phy, 1);
 101         if (!tegra->default_enable)
 102                 clk_disable(tegra->clk);
 103 }
 104
 105 static int tegra_ehci_internal_port_reset(
 106         struct ehci_hcd *ehci,
 107         u32 __iomem     *portsc_reg
 108 )
 109 {
 110         u32             temp;
 111         unsigned long   flags;
 112         int             retval = 0;
 113         int             i, tries;
 114         u32             saved_usbintr;
 115
 116         spin_lock_irqsave(&ehci->lock, flags);
 117         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
 118         /* disable USB interrupt */
 119         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 120         spin_unlock_irqrestore(&ehci->lock, flags);
 121
 122         /*
 123          * Here we have to do Port Reset at most twice for
 124          * Port Enable bit to be set.
 125          */
 126         for (i = 0; i < 2; i++) {
 127                 temp = ehci_readl(ehci, portsc_reg);
 128                 temp |= PORT_RESET;
 129                 ehci_writel(ehci, temp, portsc_reg);
 130                 mdelay(10);
 131                 temp &= ~PORT_RESET;
 132                 ehci_writel(ehci, temp, portsc_reg);
 133                 mdelay(1);
 134                 tries = 100;
 135                 do {
 136                         mdelay(1);
 137                         /*
 138                          * Up to this point, Port Enable bit is
 139                          * expected to be set after 2 ms waiting.
 140                          * USB1 usually takes extra 45 ms, for safety,
 141                          * we take 100 ms as timeout.
 142                          */
 143                         temp = ehci_readl(ehci, portsc_reg);
 144                 } while (!(temp & PORT_PE) && tries--);
 145                 if (temp & PORT_PE)
 146                         break;
 147         }
 148         if (i == 2)
 149                 retval = -ETIMEDOUT;
 150
 151         /*
 152          * Clear Connect Status Change bit if it's set.
 153          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 154          */
 155         if (temp & PORT_CSC)
 156                 ehci_writel(ehci, PORT_CSC, portsc_reg);
 157
 158         /*
 159          * Write to clear any interrupt status bits that might be set
 160          * during port reset.
 161          */
 162         temp = ehci_readl(ehci, &ehci->regs->status);
 163         ehci_writel(ehci, temp, &ehci->regs->status);
 164
 165         /* restore original interrupt enable bits */
 166         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 167         return retval;
 168 }
 169
 170 static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
 171 {
 172         struct ehci_hcd *ehci = hcd_to_ehci (hcd);
 173         struct ehci_regs __iomem *hw = ehci->regs;
 174         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 175         u32 val;
 176         irqreturn_t irq_status;
 177         bool pmc_remote_wakeup = false;
 178
 179         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
 180                 (tegra->ehci->has_hostpc)) {
 181                 /* check if there is any remote wake event */
 182                 if (tegra_usb_phy_is_remotewake_detected(tegra->phy)) {
 183                         pmc_remote_wakeup = true;
 184                         spin_lock (&ehci->lock);
 185                         usb_hcd_resume_root_hub(hcd);
 186                         spin_unlock (&ehci->lock);
 187                 }
 188         }
 189         if (tegra->phy->hotplug) {
 190                 spin_lock(&ehci->lock);
 191                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
 192                 if ((val  & TEGRA_USB_PHY_CLK_VALID_INT_STS)) {
 193                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB |
 194                                 TEGRA_USB_PHY_CLK_VALID_INT_STS;
 195                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
 196
 197                         val = readl(&hw->status);
 198                         if (!(val  & STS_PCD)) {
 199                                 spin_unlock(&ehci->lock);
 200                                 return 0;
 201                         }
 202                         val = readl(hcd->regs + TEGRA_USB_PORTSC1_OFFSET);
 203                         val &= ~(TEGRA_USB_PORTSC1_WKCN | PORT_RWC_BITS);
 204                         writel(val , (hcd->regs + TEGRA_USB_PORTSC1_OFFSET));
 205                 }
 206                 spin_unlock(&ehci->lock);
 207         }
 208
 209         irq_status = ehci_irq(hcd);
 210
 211         if (pmc_remote_wakeup) {
 212                 ehci->controller_remote_wakeup = false;
 213         }
 214
 215         if (ehci->controller_remote_wakeup) {
 216                 ehci->controller_remote_wakeup = false;
 217                 /* disable interrupts */
 218                 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 219                 tegra_usb_phy_preresume(tegra->phy, true);
 220                 tegra->port_resuming = 1;
 221         }
 222         return irq_status;
 223 }
 224
 225 static int tegra_ehci_hub_control(
 226         struct usb_hcd  *hcd,
 227         u16             typeReq,
 228         u16             wValue,
 229         u16             wIndex,
 230         char            *buf,
 231         u16             wLength
 232 )
 233 {
 234         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 235         int             ports = HCS_N_PORTS(ehci->hcs_params);
 236         u32             temp, status;
 237         u32 __iomem     *status_reg;
 238         u32             usbsts_reg;
 239
 240         unsigned long   flags;
 241         int             retval = 0;
 242         unsigned        selector;
 243         struct          tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 244         bool            hsic = false;
 245         bool do_post_resume = false;
 246
 247         if (!tegra->host_resumed) {
 248                 if (buf)
 249                         memset (buf, 0, wLength);
 250                 return retval;
 251         }
 252
 253         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
 254
 255         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 256
 257         spin_lock_irqsave(&ehci->lock, flags);
 258
 259         if (typeReq == GetPortStatus) {
 260                 temp = ehci_readl(ehci, status_reg);
 261                 if (tegra->port_resuming && !(temp & PORT_SUSPEND) &&
 262                         time_after_eq(jiffies, ehci->reset_done[wIndex-1])) {
 263                         clear_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 264                         ehci->reset_done[wIndex-1] = 0;
 265                         do_post_resume = true;
 266                 } else if (tegra->port_resuming && (temp & PORT_RESUME) &&
 267                         time_after_eq(jiffies, ehci->reset_done[wIndex-1]) ) {
 268                         do_post_resume = true;
 269                 }
 270
 271                 if (do_post_resume) {
 272                         clear_bit(wIndex-1, &ehci->resuming_ports);
 273                         tegra->port_resuming = 0;
 274                         tegra_usb_phy_postresume(tegra->phy, false);
 275                         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
 276                                 ehci->command |= CMD_RUN;
 277                                 /*
 278                                  * ehci run bit is disabled to avoid SOF.
 279                                  * 2LS WAR is executed by now enable the run bit.
 280                                  */
 281                                 ehci_writel(ehci, ehci->command,
 282                                         &ehci->regs->command);
 283                                 /* Now we can safely re-enable irqs */
 284                                 ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
 285                         }
 286                 }
 287
 288         } else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 289                 temp = ehci_readl(ehci, status_reg);
 290                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 291                         retval = -EPIPE;
 292                         goto done;
 293                 }
 294
 295                 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
 296                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
 297                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 298
 299                 /* Need a 4ms delay before the controller goes to suspend */
 300                 mdelay(4);
 301
 302                 /*
 303                  * If a transaction is in progress, there may be a delay in
 304                  * suspending the port. Poll until the port is suspended.
 305                  */
 306                 if (handshake(ehci, status_reg, PORT_SUSPEND,
 307                                                 PORT_SUSPEND, 5000))
 308                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 309
 310                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 311
 312                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
 313                         /* Disable RUN bit. */
 314                         ehci->command &= ~CMD_RUN;
 315                         ehci_writel(ehci, ehci->command,
 316                                 &ehci->regs->command);
 317                 }
 318
 319                 tegra_usb_phy_postsuspend(tegra->phy, false);
 320
 321                 goto done;
 322         }
 323
 324         /* For USB1 port we need to issue Port Reset twice internally */
 325         if (tegra->phy->instance == 0 &&
 326            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 327                 spin_unlock_irqrestore(&ehci->lock, flags);
 328                 return tegra_ehci_internal_port_reset(ehci, status_reg);
 329         }
 330
 331         /*
 332          * Tegra host controller will time the resume operation to clear the bit
 333          * when the port control state switches to HS or FS Idle. This behavior
 334          * is different from EHCI where the host controller driver is required
 335          * to set this bit to a zero after the resume duration is timed in the
 336          * driver.
 337          */
 338         else if (typeReq == ClearPortFeature &&
 339                                         wValue == USB_PORT_FEAT_SUSPEND) {
 340                 temp = ehci_readl(ehci, status_reg);
 341                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 342                         retval = -EPIPE;
 343                         goto done;
 344                 }
 345
 346                 if (!(temp & PORT_SUSPEND))
 347                         goto done;
 348
 349                 tegra->port_resuming = 1;
 350
 351                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
 352                         /* disable interrupts */
 353                         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 354                         /* Disable RUN bit. */
 355                         ehci->command &= ~CMD_RUN;
 356                         ehci_writel(ehci, ehci->command,
 357                                 &ehci->regs->command);
 358                 }
 359
 360                 /* Disable disconnect detection during port resume */
 361                 tegra_usb_phy_preresume(tegra->phy, false);
 362 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 363                 if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP) {
 364 #endif
 365                 ehci_dbg(ehci, "%s:USBSTS = 0x%x", __func__,
 366                         ehci_readl(ehci, &ehci->regs->status));
 367                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
 368                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
 369                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
 370                 udelay(20);
 371
 372                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
 373                         pr_err("%s: timeout set for STS_SRI\n", __func__);
 374
 375                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
 376                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
 377
 378                 if (handshake(ehci, &ehci->regs->status, STS_SRI, 0, 2000))
 379                         pr_err("%s: timeout clear STS_SRI\n", __func__);
 380
 381                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
 382                         pr_err("%s: timeout set STS_SRI\n", __func__);
 383
 384                 udelay(20);
 385 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 386                 }
 387 #endif
 388                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 389                 /* start resume signaling */
 390                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 391                 set_bit(wIndex-1, &ehci->resuming_ports);
 392
 393                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 394                 /* whoever resumes must GetPortStatus to complete it!! */
 395                 goto done;
 396         }
 397
 398         /* Handle port reset here */
 399         if ((hsic) && (typeReq == SetPortFeature) &&
 400                 ((wValue == USB_PORT_FEAT_RESET) || (wValue == USB_PORT_FEAT_POWER))) {
 401                 selector = wIndex >> 8;
 402                 wIndex &= 0xff;
 403                 if (!wIndex || wIndex > ports) {
 404                         retval = -EPIPE;
 405                         goto done;
 406                 }
 407                 wIndex--;
 408                 status = 0;
 409                 temp = ehci_readl(ehci, status_reg);
 410                 if (temp & PORT_OWNER)
 411                         goto done;
 412                 temp &= ~PORT_RWC_BITS;
 413
 414                 switch (wValue) {
 415                 case USB_PORT_FEAT_RESET:
 416                 {
 417                         if (temp & PORT_RESUME) {
 418                                 retval = -EPIPE;
 419                                 goto done;
 420                         }
 421                         /* line status bits may report this as low speed,
 422                         * which can be fine if this root hub has a
 423                         * transaction translator built in.
 424                         */
 425                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
 426                                         && !ehci_is_TDI(ehci) && PORT_USB11 (temp)) {
 427                                 ehci_dbg (ehci, "port %d low speed --> companion\n", wIndex + 1);
 428                                 temp |= PORT_OWNER;
 429                                 ehci_writel(ehci, temp, status_reg);
 430                         } else {
 431                                 ehci_vdbg(ehci, "port %d reset\n", wIndex + 1);
 432                                 temp &= ~PORT_PE;
 433                                 /*
 434                                 * caller must wait, then call GetPortStatus
 435                                 * usb 2.0 spec says 50 ms resets on root
 436                                 */
 437                                 ehci->reset_done[wIndex] = jiffies + msecs_to_jiffies(50);
 438                                 ehci_writel(ehci, temp, status_reg);
 439                                 if (hsic && (wIndex == 0))
 440                                         tegra_usb_phy_bus_reset(tegra->phy);
 441                         }
 442
 443                         break;
 444                 }
 445                 case USB_PORT_FEAT_POWER:
 446                 {
 447                         if (HCS_PPC(ehci->hcs_params))
 448                                 ehci_writel(ehci, temp | PORT_POWER, status_reg);
 449                         if (hsic && (wIndex == 0))
 450                                 tegra_usb_phy_bus_connect(tegra->phy);
 451                         break;
 452                 }
 453                 }
 454                 goto done;
 455         }
 456
 457         spin_unlock_irqrestore(&ehci->lock, flags);
 458
 459         /* Handle the hub control events here */
 460         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 461 done:
 462         spin_unlock_irqrestore(&ehci->lock, flags);
 463         return retval;
 464 }
 465
 466 #ifdef CONFIG_PM
 467 static void tegra_ehci_restart(struct usb_hcd *hcd, bool is_dpd)
 468 {
 469         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 470         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 471         unsigned int temp;
 472
 473         ehci->controller_resets_phy = 0;
 474         tegra_ehci_pre_reset(tegra->phy, false);
 475         ehci_reset(ehci);
 476         tegra_ehci_post_reset(tegra->phy, false);
 477
 478         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI)
 479                 ehci->controller_resets_phy = 1;
 480
 481         /* setup the frame list and Async q heads */
 482         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 483         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 484         /* setup the command register and set the controller in RUN mode */
 485         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 486 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 487         /* dont start RS here for HSIC, it will be set by bus_reset */
 488         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_HSIC)
 489 #endif
 490                 ehci->command |= CMD_RUN;
 491         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 492
 493         /* Enable the root Port Power */
 494         if (HCS_PPC(ehci->hcs_params)) {
 495                 temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
 496                 ehci_writel(ehci, temp | PORT_POWER, &ehci->regs->port_status[0]);
 497         }
 498
 499         down_write(&ehci_cf_port_reset_rwsem);
 500         if(is_dpd)
 501                 hcd->state = HC_STATE_SUSPENDED;
 502         else
 503                 hcd->state = HC_STATE_RUNNING;
 504         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 505         /* flush posted writes */
 506         ehci_readl(ehci, &ehci->regs->command);
 507         up_write(&ehci_cf_port_reset_rwsem);
 508
 509         /* Turn On Interrupts */
 510         ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
 511 }
 512 #endif
 513
 514 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 515 {
 516         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 517
 518         /* ehci_shutdown touches the USB controller registers, make sure
 519          * controller has clocks to it */
 520         if (!tegra->host_resumed)
 521                 tegra_ehci_power_up(hcd);
 522
 523         ehci_shutdown(hcd);
 524
 525         /* we are ready to shut down, powerdown the phy */
 526         tegra_ehci_power_down(hcd);
 527 }
 528
 529 static int tegra_ehci_setup(struct usb_hcd *hcd)
 530 {
 531         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 532         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 533         int retval;
 534
 535         /* EHCI registers start at offset 0x100 */
 536         ehci->caps = hcd->regs + 0x100;
 537
 538 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 539         ehci->has_hostpc = 1;
 540 #endif
 541
 542         /* switch to host mode */
 543         hcd->has_tt = 1;
 544
 545         tegra_ehci_pre_reset(tegra->phy, false);
 546
 547         retval = ehci_setup(hcd);
 548         if (retval)
 549                 return retval;
 550
 551         ehci->controller_remote_wakeup = false;
 552         tegra_ehci_post_reset(tegra->phy, false);
 553
 554         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
 555                 /*
 556                  * Resetting the controller has the side effect of resetting the PHY.
 557                  * So, never reset the controller after the calling
 558                  * tegra_ehci_reinit API.
 559                  */
 560                 ehci->controller_resets_phy = 1;
 561         }
 562
 563         return 0;
 564 }
 565
 566 struct dma_aligned_buffer {
 567         void *kmalloc_ptr;
 568         void *old_xfer_buffer;
 569         u8 data[0];
 570 };
 571
 572 static void free_dma_aligned_buffer(struct urb *urb)
 573 {
 574         struct dma_aligned_buffer *temp;
 575
 576         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 577                 return;
 578
 579         temp = container_of(urb->transfer_buffer,
 580                 struct dma_aligned_buffer, data);
 581
 582         if (usb_urb_dir_in(urb))
 583                 memcpy(temp->old_xfer_buffer, temp->data,
 584                        urb->transfer_buffer_length);
 585         urb->transfer_buffer = temp->old_xfer_buffer;
 586         kfree(temp->kmalloc_ptr);
 587
 588         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 589 }
 590
 591 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
 592 {
 593         struct dma_aligned_buffer *temp, *kmalloc_ptr;
 594         size_t kmalloc_size;
 595
 596         if (urb->num_sgs || urb->sg ||
 597             urb->transfer_buffer_length == 0 ||
 598             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 599                 return 0;
 600
 601         /* Allocate a buffer with enough padding for alignment */
 602         kmalloc_size = urb->transfer_buffer_length +
 603                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 604
 605         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 606         if (!kmalloc_ptr)
 607                 return -ENOMEM;
 608
 609         /* Position our struct dma_aligned_buffer such that data is aligned */
 610         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 611         temp->kmalloc_ptr = kmalloc_ptr;
 612         temp->old_xfer_buffer = urb->transfer_buffer;
 613         if (usb_urb_dir_out(urb))
 614                 memcpy(temp->data, urb->transfer_buffer,
 615                        urb->transfer_buffer_length);
 616         urb->transfer_buffer = temp->data;
 617
 618         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 619
 620         return 0;
 621 }
 622
 623 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 624                                       gfp_t mem_flags)
 625 {
 626         int ret;
 627
 628         ret = alloc_dma_aligned_buffer(urb, mem_flags);
 629         if (ret)
 630                 return ret;
 631
 632         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 633         if (ret)
 634                 free_dma_aligned_buffer(urb);
 635
 636         return ret;
 637 }
 638
 639 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 640 {
 641         usb_hcd_unmap_urb_for_dma(hcd, urb);
 642         free_dma_aligned_buffer(urb);
 643 }
 644
 645 static void tegra_hsic_connection_work(struct work_struct *work)
 646 {
 647         struct tegra_ehci_hcd *tegra =
 648                 container_of(work, struct tegra_ehci_hcd, work.work);
 649         if (tegra_usb_phy_is_device_connected(tegra->phy)) {
 650                 cancel_delayed_work(&tegra->work);
 651                 return;
 652         }
 653         /* Few cases HSIC device may not be connected, so   *
 654         ** skip this check after configured max re-tries.   */
 655         if (tegra->hsic_connect_retries++ > TEGRA_HSIC_CONNECTION_MAX_RETRIES)
 656                 return;
 657
 658         schedule_delayed_work(&tegra->work, jiffies + msecs_to_jiffies(50));
 659         return;
 660 }
 661
 662 void clk_timer_callback(unsigned long data)
 663 {
 664         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd*) data;
 665         unsigned long flags;
 666
 667         if (!timer_pending(&tegra->clk_timer)) {
 668                 spin_lock_irqsave(&tegra->ehci->lock, flags);
 669                 tegra->timer_event = 1;
 670                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
 671                 schedule_work(&tegra->clk_timer_work);
 672         }
 673 }
 674
 675 static void clk_timer_work_handler(struct work_struct* clk_timer_work) {
 676         struct tegra_ehci_hcd *tegra = container_of(clk_timer_work,
 677                                                 struct tegra_ehci_hcd, clk_timer_work);
 678         int ret;
 679         unsigned long flags;
 680         bool clock_enabled, timer_event;
 681
 682         spin_lock_irqsave(&tegra->ehci->lock, flags);
 683         clock_enabled = tegra->clock_enabled;
 684         timer_event = tegra->timer_event;
 685         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
 686
 687         if (timer_event) {
 688                 spin_lock_irqsave(&tegra->ehci->lock, flags);
 689                 tegra->clock_enabled = 0;
 690                 tegra->timer_event = 0;
 691                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
 692                 clk_disable_unprepare(tegra->emc_clk);
 693                 clk_disable_unprepare(tegra->sclk_clk);
 694                 return;
 695         }
 696
 697         if ((!clock_enabled)) {
 698                 ret = mod_timer(&tegra->clk_timer, jiffies + msecs_to_jiffies(2000));
 699                 if (ret)
 700                         pr_err("tegra_ehci_urb_enqueue timer modify failed \n");
 701                 clk_prepare_enable(tegra->emc_clk);
 702                 clk_prepare_enable(tegra->sclk_clk);
 703                 spin_lock_irqsave(&tegra->ehci->lock, flags);
 704                 tegra->clock_enabled = 1;
 705                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
 706         } else {
 707                 if (timer_pending(&tegra->clk_timer)) {
 708                         mod_timer_pending (&tegra->clk_timer, jiffies
 709                                                 + msecs_to_jiffies(2000));
 710                 }
 711         }
 712 }
 713
 714 static int tegra_ehci_urb_enqueue (
 715         struct usb_hcd  *hcd,
 716         struct urb      *urb,
 717         gfp_t           mem_flags)
 718 {
 719         struct tegra_ehci_hcd *pdata;
 720         int xfertype;
 721         int transfer_buffer_length;
 722         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 723         unsigned long flags;
 724         pdata = dev_get_drvdata(hcd->self.controller);
 725
 726         xfertype = usb_endpoint_type(&urb->ep->desc);
 727         transfer_buffer_length = urb->transfer_buffer_length;
 728         spin_lock_irqsave(&ehci->lock,flags);
 729         /* Turn on the USB busy hints */
 730         switch (xfertype) {
 731                 case USB_ENDPOINT_XFER_INT:
 732                 if (transfer_buffer_length < 255) {
 733                 /* Do nothing for interrupt buffers < 255 */
 734                 } else {
 735                         /* signal to set the busy hints */
 736                         schedule_work(&pdata->clk_timer_work);
 737                 }
 738                 break;
 739                 case USB_ENDPOINT_XFER_ISOC:
 740                 case USB_ENDPOINT_XFER_BULK:
 741                         /* signal to set the busy hints */
 742                         schedule_work(&pdata->clk_timer_work);
 743                 break;
 744                 case USB_ENDPOINT_XFER_CONTROL:
 745                 default:
 746                         /* Do nothing special here */
 747                 break;
 748         }
 749         spin_unlock_irqrestore(&ehci->lock,flags);
 750         return ehci_urb_enqueue(hcd, urb, mem_flags);
 751 }
 752
 753 static const struct hc_driver tegra_ehci_hc_driver = {
 754         .description            = hcd_name,
 755         .product_desc           = "Tegra EHCI Host Controller",
 756         .hcd_priv_size          = sizeof(struct ehci_hcd),
 757         .flags                  = HCD_USB2 | HCD_MEMORY,
 758
 759         /* standard ehci functions */
 760         .irq                    = tegra_ehci_irq,
 761         .start                  = ehci_run,
 762         .stop                   = ehci_stop,
 763         .urb_enqueue            = tegra_ehci_urb_enqueue,
 764         .urb_dequeue            = ehci_urb_dequeue,
 765         .endpoint_disable       = ehci_endpoint_disable,
 766         .endpoint_reset         = ehci_endpoint_reset,
 767         .get_frame_number       = ehci_get_frame,
 768         .hub_status_data        = ehci_hub_status_data,
 769         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 770         .relinquish_port        = ehci_relinquish_port,
 771         .port_handed_over       = ehci_port_handed_over,
 772
 773         /* modified ehci functions for tegra */
 774         .reset                  = tegra_ehci_setup,
 775         .shutdown               = tegra_ehci_shutdown,
 776         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
 777         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
 778         .hub_control            = tegra_ehci_hub_control,
 779 #ifdef CONFIG_PM
 780         .bus_suspend            = ehci_bus_suspend,
 781         .bus_resume             = ehci_bus_resume,
 782 #endif
 783 };
 784
 785 static int setup_vbus_gpio(struct platform_device *pdev,
 786                            struct tegra_ehci_platform_data *pdata)
 787 {
 788         int err = 0;
 789         int gpio;
 790
 791         gpio = pdata->vbus_gpio;
 792         if (!gpio_is_valid(gpio))
 793                 gpio = of_get_named_gpio(pdev->dev.of_node,
 794                                          "nvidia,vbus-gpio", 0);
 795         if (!gpio_is_valid(gpio))
 796                 return 0;
 797
 798         err = gpio_request(gpio, "vbus_gpio");
 799         if (err) {
 800                 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
 801                 return err;
 802         }
 803         err = gpio_direction_output(gpio, 1);
 804         if (err) {
 805                 dev_err(&pdev->dev, "can't enable vbus\n");
 806                 return err;
 807         }
 808
 809         return err;
 810 }
 811
 812 #ifdef CONFIG_PM
 813
 814 static int controller_suspend(struct device *dev)
 815 {
 816         struct tegra_ehci_hcd *tegra =
 817                         platform_get_drvdata(to_platform_device(dev));
 818         struct ehci_hcd *ehci = tegra->ehci;
 819         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 820         struct ehci_regs __iomem *hw = ehci->regs;
 821         unsigned long flags;
 822         int hsic = 0;
 823
 824         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
 825
 826         if (time_before(jiffies, ehci->next_statechange))
 827                 msleep(10);
 828
 829         ehci_halt(ehci);
 830 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
 831         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
 832                 /*
 833                  * Ehci run bit is disabled by now read this into command variable
 834                  * so that bus resume will not enable run bit immedialty.
 835                  * this is required for 2LS WAR on UTMIP interface.
 836                  */
 837                 tegra->ehci->command = ehci_readl(tegra->ehci,
 838                                                 &tegra->ehci->regs->command);
 839         }
 840 #endif
 841
 842         spin_lock_irqsave(&ehci->lock, flags);
 843         if (tegra->ehci->has_hostpc)
 844                 tegra->port_speed = (readl(hcd->regs + HOSTPC_REG_OFFSET) >> 25) & 0x3;
 845         else
 846                 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
 847         spin_unlock_irqrestore(&ehci->lock, flags);
 848
 849         tegra_ehci_power_down(hcd);
 850
 851         return 0;
 852 }
 853
 854 static int controller_resume(struct device *dev)
 855 {
 856         struct tegra_ehci_hcd *tegra =
 857                         platform_get_drvdata(to_platform_device(dev));
 858         struct usb_device *udev = hcd->self.root_hub;
 859         struct ehci_hcd *ehci = tegra->ehci;
 860         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 861         struct ehci_regs __iomem *hw = ehci->regs;
 862         unsigned long val;
 863         bool hsic;
 864         bool null_ulpi;
 865         bool utmip_remote_wakeup = false;
 866
 867         null_ulpi = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI);
 868         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
 869
 870         tegra_ehci_power_up(hcd);
 871         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 872
 873         if ((tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) || (hsic) ||
 874             (null_ulpi))
 875                 goto restart;
 876
 877         /* Force the phy to keep data lines in suspend state */
 878         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
 879
 880         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
 881                 (tegra->ehci->has_hostpc)) {
 882                 ehci_reset(ehci);
 883         }
 884
 885         /* Enable host mode */
 886         tdi_reset(ehci);
 887
 888         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
 889                 (tegra->ehci->has_hostpc)) {
 890                 val = readl(hcd->regs + HOSTPC_REG_OFFSET);
 891                 val &= ~HOSTPC1_DEVLC_PTS(~0);
 892                 val |= HOSTPC1_DEVLC_STS;
 893                 writel(val, hcd->regs + HOSTPC_REG_OFFSET);
 894         }
 895
 896         /* Enable Port Power */
 897         val = readl(&hw->port_status[0]);
 898         val |= PORT_POWER;
 899         writel(val, &hw->port_status[0]);
 900         udelay(10);
 901
 902         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
 903                 (tegra->ehci->has_hostpc) && (tegra->phy->remote_wakeup)) {
 904                 utmip_remote_wakeup = true;
 905         }
 906
 907         /* Check if the phy resume from LP0. When the phy resume from LP0
 908          * USB register will be reset. */
 909         if (!readl(&hw->async_next)) {
 910                 /* Program the field PTC based on the saved speed mode */
 911                 val = readl(&hw->port_status[0]);
 912                 val &= ~PORT_TEST(~0);
 913                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
 914                         val |= PORT_TEST_FORCE;
 915                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
 916                         val |= PORT_TEST(6);
 917                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 918                         val |= PORT_TEST(7);
 919                 writel(val, &hw->port_status[0]);
 920                 udelay(10);
 921
 922                 /* Disable test mode by setting PTC field to NORMAL_OP */
 923                 val = readl(&hw->port_status[0]);
 924                 val &= ~PORT_TEST(~0);
 925                 writel(val, &hw->port_status[0]);
 926                 udelay(10);
 927         }
 928
 929         /* Poll until CCS is enabled */
 930         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
 931                                                  PORT_CONNECT, 2000)) {
 932                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
 933                 goto restart;
 934         }
 935
 936         /* Poll until PE is enabled */
 937         if (handshake(ehci, &hw->port_status[0], PORT_PE,
 938                                                  PORT_PE, 2000)) {
 939                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
 940                 goto restart;
 941         }
 942
 943         /* Clear the PCI status, to avoid an interrupt taken upon resume */
 944         val = readl(&hw->status);
 945         val |= STS_PCD;
 946         writel(val, &hw->status);
 947
 948         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
 949         val = readl(&hw->port_status[0]);
 950         if ((val & PORT_POWER) && (val & PORT_PE)) {
 951                 val |= PORT_SUSPEND;
 952                 writel(val, &hw->port_status[0]);
 953
 954                 /* Need a 4ms delay before the controller goes to suspend */
 955                 mdelay(4);
 956
 957                 /* Wait until port suspend completes */
 958                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
 959                                                          PORT_SUSPEND, 1000)) {
 960                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
 961                                                                 __func__);
 962                         goto restart;
 963                 }
 964         }
 965
 966         tegra_ehci_phy_restore_end(tegra->phy);
 967         if (utmip_remote_wakeup) {
 968                 ehci->command |= CMD_RUN;
 969                 ehci_writel(ehci, ehci->command, &ehci->regs->command);
 970         }
 971         goto done;
 972
 973  restart:
 974         if (null_ulpi) {
 975                 bool LP0 = !readl(&hw->async_next);
 976
 977                 if (LP0) {
 978                         static int cnt = 1;
 979
 980                         pr_info("LP0 restart %d\n", cnt++);
 981                         tegra_ehci_phy_restore_start(tegra->phy,
 982                                                      tegra->port_speed);
 983                 }
 984
 985                 val = readl(&hw->port_status[0]);
 986                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
 987                         tegra_ehci_restart(hcd, is_dpd);
 988                 }
 989
 990                 if (LP0)
 991                         tegra_ehci_phy_restore_end(tegra->phy);
 992
 993                 return 0;
 994         }
 995
 996         if ((tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) && (!hsic))
 997                 tegra_ehci_phy_restore_end(tegra->phy);
 998         if (hsic) {
 999                 val = readl(&hw->port_status[0]);
1000                 if (!((val & PORT_POWER) && (val & PORT_PE)))
1001                         tegra_ehci_restart(hcd, false);
1002
1003                 tegra_usb_phy_bus_idle(tegra->phy);
1004                 tegra->hsic_connect_retries = 0;
1005                 if (!tegra_usb_phy_is_device_connected(tegra->phy))
1006                         schedule_delayed_work(&tegra->work, 50);
1007         } else {
1008                 tegra_ehci_restart(hcd, false);
1009         }
1010
1011  done:
1012         return 0;
1013 }
1014
1015 static int tegra_ehci_suspend(struct device *dev)
1016 {
1017         struct tegra_ehci_hcd *tegra =
1018                         platform_get_drvdata(to_platform_device(dev));
1019         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1020         int rc = 0;
1021         u32 val;
1022
1023         pm_runtime_resume();
1024
1025         if (tegra->phy->hotplug) {
1026                 /* Disable PHY clock valid interrupts while going into suspend*/
1027                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
1028                 val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB;
1029                 writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
1030         }
1031
1032         /*
1033          * When system sleep is supported and USB controller wakeup is
1034          * implemented: If the controller is runtime-suspended and the
1035          * wakeup setting needs to be changed, call pm_runtime_resume().
1036          */
1037         if (HCD_HW_ACCESSIBLE(hcd))
1038                 rc = controller_suspend(dev);
1039         if (tegra->default_enable)
1040                 clk_disable(tegra->clk);
1041         return rc;
1042 }
1043
1044 static int tegra_ehci_resume(struct device *dev)
1045 {
1046         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1047         int rc;
1048
1049         if (tegra->default_enable)
1050                 clk_enable(tegra->clk);
1051
1052         rc = controller_resume(dev);
1053         if (rc == 0) {
1054                 pm_runtime_disable(dev);
1055                 pm_runtime_set_active(dev);
1056                 pm_runtime_enable(dev);
1057         }
1058         return rc;
1059 }
1060
1061 static int tegra_ehci_runtime_suspend(struct device *dev)
1062 {
1063         return controller_suspend(dev);
1064 }
1065
1066 static int tegra_ehci_runtime_resume(struct device *dev)
1067 {
1068         return controller_resume(dev);
1069 }
1070
1071 static const struct dev_pm_ops tegra_ehci_pm_ops = {
1072         .suspend        = tegra_ehci_suspend,
1073         .resume         = tegra_ehci_resume,
1074         .runtime_suspend = tegra_ehci_runtime_suspend,
1075         .runtime_resume = tegra_ehci_runtime_resume,
1076 };
1077
1078 #endif
1079
1080 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
1081
1082 static int tegra_ehci_probe(struct platform_device *pdev)
1083 {
1084         struct resource *res;
1085         struct usb_hcd *hcd;
1086         struct tegra_ehci_hcd *tegra;
1087         struct tegra_ehci_platform_data *pdata;
1088         int err = 0;
1089         int irq;
1090         int instance = pdev->id;
1091
1092         pdata = pdev->dev.platform_data;
1093         if (!pdata) {
1094                 dev_err(&pdev->dev, "Platform data missing\n");
1095                 return -EINVAL;
1096         }
1097
1098         /* Right now device-tree probed devices don't get dma_mask set.
1099          * Since shared usb code relies on it, set it here for now.
1100          * Once we have dma capability bindings this can go away.
1101          */
1102         if (!pdev->dev.dma_mask)
1103                 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
1104
1105         setup_vbus_gpio(pdev, pdata);
1106
1107         tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
1108                              GFP_KERNEL);
1109         if (!tegra)
1110                 return -ENOMEM;
1111
1112         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
1113                                         dev_name(&pdev->dev));
1114         if (!hcd) {
1115                 dev_err(&pdev->dev, "Unable to create HCD\n");
1116                 return -ENOMEM;
1117         }
1118
1119         platform_set_drvdata(pdev, tegra);
1120         tegra->default_enable = pdata->default_enable;
1121
1122         tegra->clk = devm_clk_get(&pdev->dev, NULL);
1123         if (IS_ERR(tegra->clk)) {
1124                 dev_err(&pdev->dev, "Can't get ehci clock\n");
1125                 err = PTR_ERR(tegra->clk);
1126                 goto fail_clk;
1127         }
1128
1129         err = clk_prepare_enable(tegra->clk);
1130         if (err)
1131                 goto fail_clk;
1132
1133         tegra->sclk_clk = devm_clk_get(&pdev->dev, "sclk");
1134         if (IS_ERR(tegra->sclk_clk)) {
1135                 dev_err(&pdev->dev, "Can't get sclk clock\n");
1136                 err = PTR_ERR(tegra->sclk_clk);
1137                 goto fail_sclk_clk;
1138         }
1139
1140         clk_prepare_enable(tegra->sclk_clk);
1141         clk_set_rate(tegra->sclk_clk, 80000000);
1142
1143         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1144         if (IS_ERR(tegra->emc_clk)) {
1145                 dev_err(&pdev->dev, "Can't get emc clock\n");
1146                 err = PTR_ERR(tegra->emc_clk);
1147                 goto fail_emc_clk;
1148         }
1149         init_timer(&tegra->clk_timer);
1150         tegra->clk_timer.function = clk_timer_callback;
1151         tegra->clk_timer.data = (unsigned long) tegra;
1152
1153 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1154         /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */
1155         clk_set_rate(tegra->emc_clk, 300000000);
1156 #else
1157         /* Set DDR busy hints to 100MHz. For Tegra 3x SOC DDR rate equals to EMC rate */
1158         clk_set_rate(tegra->emc_clk, 100000000);
1159 #endif
1160
1161         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1162         if (!res) {
1163                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1164                 err = -ENXIO;
1165                 goto fail_io;
1166         }
1167         hcd->rsrc_start = res->start;
1168         hcd->rsrc_len = resource_size(res);
1169         hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1170         if (!hcd->regs) {
1171                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1172                 err = -ENOMEM;
1173                 goto fail_io;
1174         }
1175
1176         /* This is pretty ugly and needs to be fixed when we do only
1177          * device-tree probing. Old code relies on the platform_device
1178          * numbering that we lack for device-tree-instantiated devices.
1179          */
1180         if (instance < 0) {
1181                 switch (res->start) {
1182                 case TEGRA_USB_BASE:
1183                         instance = 0;
1184                         break;
1185                 case TEGRA_USB2_BASE:
1186                         instance = 1;
1187                         break;
1188                 case TEGRA_USB3_BASE:
1189                         instance = 2;
1190                         break;
1191                 default:
1192                         err = -ENODEV;
1193                         dev_err(&pdev->dev, "unknown usb instance\n");
1194                         goto fail_io;
1195                 }
1196         }
1197
1198         INIT_DELAYED_WORK(&tegra->work, tegra_hsic_connection_work);
1199
1200         INIT_WORK(&tegra->clk_timer_work, clk_timer_work_handler);
1201
1202         tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
1203                                         pdata->phy_config,
1204                                         TEGRA_USB_PHY_MODE_HOST, pdata->phy_type);
1205         if (IS_ERR(tegra->phy)) {
1206                 dev_err(&pdev->dev, "Failed to open USB phy\n");
1207                 err = -ENXIO;
1208                 goto fail_io;
1209         }
1210         tegra->phy->hotplug = pdata->hotplug;
1211
1212         usb_phy_init(&tegra->phy->u_phy);
1213
1214         err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
1215         if (err) {
1216                 dev_err(&pdev->dev, "Failed to power on the phy\n");
1217                 goto fail;
1218         }
1219
1220         tegra->host_resumed = 1;
1221         tegra->ehci = hcd_to_ehci(hcd);
1222
1223         irq = platform_get_irq(pdev, 0);
1224         if (!irq) {
1225                 dev_err(&pdev->dev, "Failed to get IRQ\n");
1226                 err = -ENODEV;
1227                 goto fail;
1228         }
1229         tegra->irq = irq;
1230
1231         if (pdata->operating_mode == TEGRA_USB_OTG) {
1232                 tegra->transceiver =
1233                         devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
1234                 if (!IS_ERR(tegra->transceiver))
1235                         otg_set_host(tegra->transceiver->otg, &hcd->self);
1236         }
1237
1238         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
1239         if (err) {
1240                 dev_err(&pdev->dev, "Failed to add USB HCD error = %d\n", err);
1241                 goto fail;
1242         }
1243
1244         err = enable_irq_wake(tegra->irq);
1245         if (err < 0) {
1246                 dev_warn(&pdev->dev,
1247                         "Couldn't enable USB host mode wakeup, irq=%d, "
1248                         "error=%d\n", tegra->irq, err);
1249                 err = 0;
1250                 tegra->irq = 0;
1251         }
1252
1253         pm_runtime_set_active(&pdev->dev);
1254         pm_runtime_get_noresume(&pdev->dev);
1255
1256         /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
1257         /* if (!pdata->power_down_on_bus_suspend) */
1258                 pm_runtime_forbid(&pdev->dev);
1259         pm_runtime_enable(&pdev->dev);
1260         pm_runtime_put_sync(&pdev->dev);
1261         return err;
1262
1263 fail:
1264         if (!IS_ERR(tegra->transceiver))
1265                 otg_set_host(tegra->transceiver->otg, NULL);
1266         usb_phy_shutdown(&tegra->phy->u_phy);
1267 fail_io:
1268         clk_disable_unprepare(tegra->emc_clk);
1269 fail_emc_clk:
1270         clk_disable_unprepare(tegra->sclk_clk);
1271 fail_sclk_clk:
1272         clk_disable_unprepare(tegra->clk);
1273 fail_clk:
1274         usb_put_hcd(hcd);
1275         return err;
1276 }
1277
1278 static int tegra_ehci_remove(struct platform_device *pdev)
1279 {
1280         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1281         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1282
1283         /* make sure controller is on as we will touch its registers */
1284         if (!tegra->host_resumed)
1285                 tegra_ehci_power_up(hcd, true);
1286
1287         pm_runtime_get_sync(&pdev->dev);
1288         pm_runtime_disable(&pdev->dev);
1289         pm_runtime_put_noidle(&pdev->dev);
1290
1291         if (!IS_ERR(tegra->transceiver))
1292                 otg_set_host(tegra->transceiver->otg, NULL);
1293
1294         /* Turn Off Interrupts */
1295         ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
1296         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1297         if (tegra->irq)
1298                 disable_irq_wake(tegra->irq);
1299         usb_remove_hcd(hcd);
1300         usb_put_hcd(hcd);
1301         cancel_delayed_work(&tegra->work);
1302         tegra_usb_phy_power_off(tegra->phy);
1303         usb_phy_shutdown(&tegra->phy->u_phy);
1304
1305         del_timer_sync(&tegra->clk_timer);
1306
1307         clk_disable_unprepare(tegra->clk);
1308
1309         if (tegra->clock_enabled) {
1310                 clk_disable_unprepare(tegra->sclk_clk);
1311                 clk_disable_unprepare(tegra->emc_clk);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
1318 {
1319         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1320         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1321
1322         if (hcd->driver->shutdown)
1323                 hcd->driver->shutdown(hcd);
1324 }
1325
1326 static struct of_device_id tegra_ehci_of_match[] = {
1327         { .compatible = "nvidia,tegra20-ehci", },
1328         { },
1329 };
1330
1331 static struct platform_driver tegra_ehci_driver = {
1332         .probe          = tegra_ehci_probe,
1333         .remove         = tegra_ehci_remove,
1334         .shutdown       = tegra_ehci_hcd_shutdown,
1335         .driver         = {
1336                 .name   = "tegra-ehci",
1337                 .of_match_table = tegra_ehci_of_match,
1338 #ifdef CONFIG_PM
1339                 .pm     = &tegra_ehci_pm_ops,
1340 #endif
1341         }
1342 };