5 #include <stdint.h> // uintX_t
10 /*masked fields macros*/
12 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
15 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
18 /* Hardware specific */
20 #define GPIOC_reg 0x54
23 #define ADCTRL_reg 0x00
24 #define ADDATA0_reg 0x00
25 #define ADDATA1_reg 0x02
26 #define ADDATA2_reg 0x04
27 #define ADDATA3_reg 0x06
28 #define ADDATA4_reg 0x08
29 #define ADDATA5_reg 0x0a
30 #define ADDATA6_reg 0x0c
31 #define ADDATA7_reg 0x0e
32 #define ADSTART_reg 0x20
46 #define CTR0STATUS_reg 0x00
47 #define CTR1STATUS_reg 0x10
48 #define CTR2STATUS_reg 0x20
49 #define CTR3STATUS_reg 0x30
50 #define CTR4STATUS_reg 0x40
52 #define CTR_STATUS_RUNNING_mask 0x00000001
53 #define CTR_STATUS_OUTPUT_mask 0x00000002
55 #define CTR0MODE_reg 0x00
56 #define CTR1MODE_reg 0x10
57 #define CTR2MODE_reg 0x20
58 #define CTR3MODE_reg 0x30
59 #define CTR4MODE_reg 0x40
61 #define CTR_MODE_COUNT_DIR_mask 0x00000001
62 enum {CTR_MODE_COUNT_DIR_DOWN, CTR_MODE_COUNT_DIR_UP};
63 #define CTR_MODE_REPETITION_mask 0x00000002
64 enum {CTR_MODE_REPETITION_DISABLED, CTR_MODE_REPETITION_ENABLED};
65 #define CTR_MODE_LOAD_TOGGLE_mask 0x00000004
66 enum {CTR_MODE_LOAD_TOGGLE_DISABLED /* reload from A only */,
67 CTR_MODE_LOAD_TOGGLE_ENABLED /* alter A and B */};
68 #define CTR_MODE_OUTPUT_TOGGLE_mask 0x00000008
69 enum {CTR_MODE_OUTPUT_TOGGLE_DISABLED /* output changed at terminal count */,
70 CTR_MODE_OUTPUT_TOGGLE_ENABLED /* output is toggled at terminal count */};
71 #define CTR_MODE_OUTPUT_CONTROL_mask 0x00000030
72 enum {CTR_MODE_OUTPUT_CONTROL_DIRECT /* direct output */,
73 CTR_MODE_OUTPUT_CONTROL_INVERTED /* inverted output */,
74 CTR_MODE_OUTPUT_CONTROL_FORCE_LO /* force output low */,
75 CTR_MODE_OUTPUT_CONTROL_FORCE_HI /* force output high */};
76 #define CTR_MODE_TRIGGER_SOURCE_mask 0x000000C0
77 enum {CTR_MODE_TRIGGER_SOURCE_DISABLED /* trigger disabled */,
78 CTR_MODE_TRIGGER_SOURCE_TXIN /* trigger by counter input (TxIN) */,
79 CTR_MODE_TRIGGER_SOURCE_BY_PREV /* trigger by counter n-1 output */,
80 CTR_MODE_TRIGGER_SOURCE_BY_NEXT /* trigger by counter n+1 output */};
81 #define CTR_MODE_TRIGGER_TYPE_mask 0x00000300
82 enum {CTR_MODE_TRIGGER_TYPE_DISABLED /* trigger disabled */,
83 CTR_MODE_TRIGGER_TYPE_BY_RE /* by rising edge of trigger signal */,
84 CTR_MODE_TRIGGER_TYPE_BY_FE /* by falling edge of trigger signal */,
85 CTR_MODE_TRIGGER_TYPE_BY_BOTH /* by either edge of trigger signal */};
86 #define CTR_MODE_RETRIGGER_mask 0x00000400
87 enum {CTR_MODE_RETRIGGER_DISABLED /* counter can be triggered only when stopped */,
88 CTR_MODE_RETRIGGER_ENABLED /* counter can be retriggered when running */};
89 #define CTR_MODE_GATE_SOURCE_mask 0x00001800
90 enum {CTR_MODE_GATE_SOURCE_SET_HIGH /* gate set high/not gated */,
91 CTR_MODE_GATE_SOURCE_BY_TXIN /* gated by counter input (TxIN) */,
92 CTR_MODE_GATE_SOURCE_BY_PREV /* gated by counter n-1 output */,
93 CTR_MODE_GATE_SOURCE_BY_NEXT /* gated by counter n+1 output */};
94 #define CTR_MODE_GATE_POLARITY_mask 0x00002000
95 enum {CTR_MODE_GATE_POLARITY_LOW /* low level of gate signal disables counting */,
96 CTR_MODE_GATE_POLARITY_HIGH /* high level of gate signal disables counting */};
97 #define CTR_MODE_CLOCK_SOURCE_mask 0x0003C000
98 enum {CTR_MODE_CLOCK_SOURCE_50MHZ /* 50 MHz internal clock */,
99 CTR_MODE_CLOCK_SOURCE_10MHZ /* 10 MHz internal clock */,
100 CTR_MODE_CLOCK_SOURCE_1MHZ /* 1 MHz internal clock */,
101 CTR_MODE_CLOCK_SOURCE_100KHZ /* 100 kHz internal clock */,
102 CTR_MODE_CLOCK_SOURCE_res1 /* reserved */,
103 CTR_MODE_CLOCK_SOURCE_TXIN_RE /* counter input (TxIN) rising edge */,
104 CTR_MODE_CLOCK_SOURCE_TXIN_FE /* counter input (TxIN) falling edge */,
105 CTR_MODE_CLOCK_SOURCE_TXIN_BOTH /* counter input (TxIN) either edge */,
106 CTR_MODE_CLOCK_SOURCE_res2 /* reserved */,
107 CTR_MODE_CLOCK_SOURCE_PREV_RE /* counter n-1 output rising edge */,
108 CTR_MODE_CLOCK_SOURCE_PREV_FE /* counter n-1 output falling edge */,
109 CTR_MODE_CLOCK_SOURCE_PREV_BOTH /* counter n-1 output either edge */,
110 CTR_MODE_CLOCK_SOURCE_res3 /* reserved */,
111 CTR_MODE_CLOCK_SOURCE_NEXT_RE /* counter n+1 output rising edge */,
112 CTR_MODE_CLOCK_SOURCE_NEXT_FE /* counter n+1 output falling edge */,
113 CTR_MODE_CLOCK_SOURCE_NEXT_BOTH /* counter n+1 output either edge */};
114 #define CTR_MODE_ADTRIGSRC_mask 0x40000000 /* Implemented in CTR4MODE register only */
115 enum {CTR_MODE_ADTRIGSRC_OUTPUT_FE /* ADC triggers by falling edge of counter 4 output */,
116 CTR_MODE_ADTRIGSRC_EXTERNAL_INPUT /* triggers by falling edge of external trigger input. */};
117 #define CTR_MODE_CTR4INTSRC_mask 0x80000000 /* Implemented in CTR4MODE register only */
118 enum {CTR_MODE_CTR4INTSRC_OUTPUT_FE /* interrupts by falling edge of counter 4 output */,
119 CTR_MODE_CTR4INTSRC_EXTERNAL_INPUT/* interrupts by falling edge of external trigger input */};
121 #define CTR0_reg 0x04
122 #define CTR1_reg 0x14
123 #define CTR2_reg 0x24
124 #define CTR3_reg 0x34
125 #define CTR4_reg 0x44
127 #define CTR0A_reg 0x04
128 #define CTR1A_reg 0x14
129 #define CTR2A_reg 0x24
130 #define CTR3A_reg 0x34
131 #define CTR4A_reg 0x44
133 #define CTR0B_reg 0x08
134 #define CTR1B_reg 0x18
135 #define CTR2B_reg 0x28
136 #define CTR3B_reg 0x38
138 #define CTRXCTRL_reg 0x60
140 #define CTRXCTRL_CHANNEL_SHIFT 6
142 #define CTRXCTRL_CTR0START_mask 0x00000001
143 #define CTRXCTRL_CTR0STOP_mask 0x00000002
144 #define CTRXCTRL_CTR0LOAD_mask 0x00000004
145 #define CTRXCTRL_CTR0RESET_mask 0x00000008
146 #define CTRXCTRL_CTR0TSET_mask 0x00000010
147 #define CTRXCTRL_CTR0TRESET_mask 0x00000020
149 #define CTRXCTRL_CTR1START_mask 0x00000040
150 #define CTRXCTRL_CTR1STOP_mask 0x00000080
151 #define CTRXCTRL_CTR1LOAD_mask 0x00000100
152 #define CTRXCTRL_CTR1RESET_mask 0x00000200
153 #define CTRXCTRL_CTR1TSET_mask 0x00000400
154 #define CTRXCTRL_CTR1TRESET_mask 0x00000800
156 #define CTRXCTRL_CTR2START_mask 0x00001000
157 #define CTRXCTRL_CTR2STOP_mask 0x00002000
158 #define CTRXCTRL_CTR2LOAD_mask 0x00004000
159 #define CTRXCTRL_CTR2RESET_mask 0x00008000
160 #define CTRXCTRL_CTR2TSET_mask 0x00010000
161 #define CTRXCTRL_CTR2TRESET_mask 0x00020000
163 #define CTRXCTRL_CTR3START_mask 0x00040000
164 #define CTRXCTRL_CTR3STOP_mask 0x00080000
165 #define CTRXCTRL_CTR3LOAD_mask 0x00100000
166 #define CTRXCTRL_CTR3RESET_mask 0x00200000
167 #define CTRXCTRL_CTR3TSET_mask 0x00400000
168 #define CTRXCTRL_CTR3TRESET_mask 0x00800000
170 #define CTRXCTRL_CTR4START_mask 0x01000000
171 #define CTRXCTRL_CTR4STOP_mask 0x02000000
172 #define CTRXCTRL_CTR4LOAD_mask 0x04000000
173 #define CTRXCTRL_CTR4RESET_mask 0x08000000
174 #define CTRXCTRL_CTR4TSET_mask 0x10000000
175 #define CTRXCTRL_CTR4TRESET_mask 0x20000000
177 #define IRCSTATUS_reg 0x6C
178 #define IRCCTRL_reg 0x6C
179 #define IRC0_reg 0x70
180 #define IRC1_reg 0x74
181 #define IRC2_reg 0x78
182 #define IRC3_reg 0x7C
184 #define IRCCTRL_IRC0MODE_mask 0x00000003
185 #define IRCCTRL_IRC0COUNT_mask 0x0000000C
186 #define IRCCTRL_IRC0RESET_mask 0x00000070
187 #define IRCCTRL_IRC0FILTER_mask 0x00000080
189 #define IRCCTRL_IRC1MODE_mask 0x00000300
190 #define IRCCTRL_IRC1COUNT_mask 0x00000C00
191 #define IRCCTRL_IRC1RESET_mask 0x00007000
192 #define IRCCTRL_IRC1FILTER_mask 0x00008000
194 #define IRCCTRL_IRC2MODE_mask 0x00030000
195 #define IRCCTRL_IRC2COUNT_mask 0x000C0000
196 #define IRCCTRL_IRC2RESET_mask 0x00700000
197 #define IRCCTRL_IRC2FILTER_mask 0x00800000
199 #define IRCCTRL_IRC3MODE_mask 0x03000000
200 #define IRCCTRL_IRC3COUNT_mask 0x0C000000
201 #define IRCCTRL_IRC3RESET_mask 0x70000000
202 #define IRCCTRL_IRC3FILTER_mask 0x80000000
204 #define IRCCTRL_CHANNEL_SHIFT 8
206 #define IRCCTRL_MODE_mask(ch) (0x03<<((ch)*IRCCTRL_CHANNEL_SHIFT))
207 #define IRCCTRL_COUNT_mask(ch) (0x0C<<((ch)*IRCCTRL_CHANNEL_SHIFT))
208 #define IRCCTRL_RESET_mask(ch) (0x70<<((ch)*IRCCTRL_CHANNEL_SHIFT))
209 #define IRCCTRL_FILTER_mask(ch) (0x80<<((ch)*IRCCTRL_CHANNEL_SHIFT))
211 #define IRCCTRL_MODE_IRC 0
212 #define IRCCTRL_MODE_BIDIR_RE 1
213 #define IRCCTRL_MODE_BIDIR_FE 2
214 #define IRCCTRL_MODE_BIDIR_BOTH 3
216 #define IRCCTRL_COUNT_ENABLED 0
217 #define IRCCTRL_COUNT_DISABLED 1
218 #define IRCCTRL_COUNT_IF_IDX_LO 2
219 #define IRCCTRL_COUNT_IF_IDX_HI 3
221 #define IRCCTRL_RESET_DISABLED 0
222 #define IRCCTRL_RESET_ALWAYS 1
223 #define IRCCTRL_RESET_IF_IDX_LO 2
224 #define IRCCTRL_RESET_IF_IDX_HI 3
225 #define IRCCTRL_RESET_IF_IDX_RE 4
226 #define IRCCTRL_RESET_IF_IDX_FE 5
227 #define IRCCTRL_RESET_IF_IDX_BOTH 6
229 #define IRCSTATUS_IRC0INDEX_mask 0x00000001
230 #define IRCSTATUS_IRC1INDEX_mask 0x00000100
231 #define IRCSTATUS_IRC2INDEX_mask 0x00000100
232 #define IRCSTATUS_IRC3INDEX_mask 0x00000100
234 #define IRCSTATUS_CHANNEL_SHIFT 8
236 #define IRCSTATUS_INDEX_mask(ch) (0x01<<((ch)*IRCSTATUS_CHANNEL_SHIFT))
238 #define GPIOC_DACEN_mask (1 << 26)
239 #define GPIOC_LDAC_mask (1 << 23)
240 #define GPIOC_EOLC_mask (1 << 17)
242 #define MFST2REG(mfst, bar_num, reg_offs) \
243 ((void *)(mfst->bar##bar_num.virt_addr + (reg_offs)))
246 typedef struct bar_mapping_t {
256 typedef enum {DA0, DA1, DA2, DA3, DA4, DA5, DA6, DA7} dac_channel_t;
257 typedef enum {AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7} adc_channel_t;
259 typedef struct mf624_state_t {
266 int ADC_enabled; // Which ADCs are enabled
271 //extern mf624_state_t mf624_state;
272 extern mf624_state_t* mfst;
274 static uint32_t dac_channel2reg[] = {
285 static uint32_t adc_channel2reg[] = {
296 static inline int16_t mf624_read16(void *ptr)
298 return *(volatile uint16_t*)ptr;
301 static inline int32_t mf624_read32(void *ptr)
303 return *(volatile uint32_t*) ptr;
306 static inline void mf624_write16(uint16_t val, void *ptr)
308 *(volatile uint16_t*) ptr = val;
311 static inline void mf624_write32(uint32_t val, void *ptr)
313 *(volatile uint32_t*) ptr = val;
316 extern void DIO_write(mf624_state_t* mfst, int16_t val);
318 extern uint16_t DIO_read(mf624_state_t* mfst);
320 extern void DAC_enable(mf624_state_t* mfst);
322 extern int DAC_write(mf624_state_t* mfst, dac_channel_t channel, int val);
324 extern int ADC_enable(mf624_state_t* mfst, adc_channel_t channel);
326 extern double ADC_read(mf624_state_t* mfst, adc_channel_t channel);
328 extern uint32_t IRC_mode_change(mf624_state_t* mfst, uint32_t change_mask, uint32_t change_val);
330 int mf624_init(SimStruct *S);
331 int mf624_check(SimStruct *S);