+++ /dev/null
-# PF: TEGRA2
-# PFDESCR: NVIDIA Tegra 2xx platform
-# PFSELECT: CAN_ARM_CPU_CORTEX_A9 CAN_ARM_CACHE_L2CXX0
-# PFDEPENDS: ARM
-
-choice
- prompt "Platform Timer"
- default PF_TEGRA_TIMER_MP
-
-config PF_TEGRA_TIMER_MP
- bool "MP timer"
- help
- ARM local-core multi-processor timer.
-
-config PF_TEGRA_TIMER_TMR
- bool "TMR timer"
- help
- Single broadcasting timer.
-
-endchoice
+++ /dev/null
-# vim:set ft=make:
-
-PREPROCESS_PARTS += tegra2 16550 pic_gic generic_tickless_idle
-PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_MP) += mptimer
-PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_TMR) += tegra_timer_tmr
-RAM_PHYS_BASE := 0x0
-INTERFACES_KERNEL += gic
-MPCORE_PHYS_BASE := 0x50040000
-
-uart_IMPL += uart-16550 uart-16550-arm-tegra2
-config_IMPL += config-arm-tegra2
-mem_layout_IMPL += mem_layout-arm-tegra2
-pic_IMPL += pic-gic pic-arm-tegra2
-bootstrap_IMPL += bootstrap-arm-tegra2
-timer_IMPL += $(if $(CONFIG_PF_TEGRA_TIMER_MP),timer-arm-tegra2 timer-arm-mptimer)
-timer_IMPL += $(if $(CONFIG_PF_TEGRA_TIMER_TMR),timer-arm-tegra2)
-timer_tick_IMPL += $(if $(CONFIG_PF_TEGRA_TIMER_MP),timer_tick-single-vector)
-timer_tick_IMPL += $(if $(CONFIG_PF_TEGRA_TIMER_TMR),timer_tick-broadcast)
-kernel_uart_IMPL += kernel_uart-arm-tegra2
-reset_IMPL += reset-arm-tegra2
-clock_IMPL += clock-generic
-platform_control_IMPL += platform_control-arm-tegra2
-outer_cache_IMPL += outer_cache-arm-tegra2
+++ /dev/null
-INTERFACE [arm && tegra2]:
-
-namespace Bootstrap {
-enum { Cache_flush_area = 0, };
-}
+++ /dev/null
-INTERFACE[arm && tegra2]:
-
-#define TARGET_NAME "Tegra2"
+++ /dev/null
-INTERFACE:
-
-// On ARM the MMIO for the uart is accessible before the MMU is fully up
-EXTENSION class Kernel_uart { enum { Bsp_init_mode = Init_before_mmu }; };
-
-IMPLEMENTATION [arm && tegra2 && serial]:
-
-#include "mem_layout.h"
-#include "kmem.h"
-IMPLEMENT
-bool Kernel_uart::startup(unsigned port, int /*irq*/)
-{
- return Uart::startup(Kmem::mmio_remap(Mem_layout::Uart_phys_base), 122);
-}
+++ /dev/null
-INTERFACE [arm && tegra2]:
-
-EXTENSION class Mem_layout
-{
-public:
- enum Phys_layout_tegra2 : Address
- {
- Mp_scu_phys_base = 0x50040000,
- L2cxx0_phys_base = 0x50043000,
-
- Gic_cpu_phys_base = 0x50040100,
- Gic_dist_phys_base = 0x50041000,
- Gic2_cpu_phys_base = 0x50020000,
- Gic2_dist_phys_base = 0x50021000,
-
- Tmr_phys_base = 0x60005000,
- Clock_reset_phys_base = 0x60006000,
- Uart_phys_base = 0x70006300,
- };
-};
+++ /dev/null
-IMPLEMENTATION [arm && tegra2 && outer_cache_l2cxx0]:
-
-IMPLEMENT
-Mword
-Outer_cache::platform_init(Mword aux_control)
-{
- l2cxx0->write<Mword>(0x331, L2cxx0::TAG_RAM_CONTROL);
- l2cxx0->write<Mword>(0x441, L2cxx0::DATA_RAM_CONTROL);
-
- aux_control &= 0x8200c3fe;
- aux_control |= (1 << 0) // Full Line of Zero Enable
- | (4 << 17) // 128kb waysize
- | (1 << 28) // data prefetch
- | (1 << 29) // insn prefetch
- | (1 << 30) // early BRESP enable
- ;
- return aux_control;
-}
+++ /dev/null
-INTERFACE [arm && pic_gic && tegra2]:
-
-#include "gic.h"
-
-//-------------------------------------------------------------------
-IMPLEMENTATION [arm && pic_gic && tegra2]:
-
-#include "irq_chip.h"
-#include "irq_mgr_multi_chip.h"
-#include "gic.h"
-#include "kmem.h"
-
-IMPLEMENT FIASCO_INIT
-void Pic::init()
-{
- typedef Irq_mgr_multi_chip<8> M;
-
- M *m = new Boot_object<M>(1);
-
- gic.construct(Kmem::mmio_remap(Mem_layout::Gic_cpu_phys_base),
- Kmem::mmio_remap(Mem_layout::Gic_dist_phys_base));
- m->add_chip(0, gic, gic->nr_irqs());
-
- Irq_mgr::mgr = m;
-}
-
-IMPLEMENT inline
-Pic::Status Pic::disable_all_save()
-{ return 0; }
-
-IMPLEMENT inline
-void Pic::restore_all(Status)
-{}
-
-//-------------------------------------------------------------------
-IMPLEMENTATION [arm && mp && pic_gic && tegra2]:
-
-PUBLIC static
-void Pic::init_ap(Cpu_number)
-{
- gic->init_ap();
-}
+++ /dev/null
-INTERFACE [arm && mp && tegra2]:
-
-#include "mem_layout.h"
-
-EXTENSION class Platform_control
-{
-private:
- enum
- {
- Reset_vector_addr = 0x6000f100,
- Clk_rst_ctrl_clk_cpu_cmplx = 0x6000604c,
- Clk_rst_ctrl_rst_cpu_cmplx_clr = 0x60006344,
- Unhalt_addr = 0x60007014,
- };
-
- static Mword _orig_reset_vector;
-};
-
-IMPLEMENTATION [arm && mp && tegra2]:
-
-#include "io.h"
-#include "kmem.h"
-#include <cstdlib>
-
-Mword Platform_control::_orig_reset_vector;
-
-PRIVATE static
-void Platform_control::reset_orig_reset_vector()
-{
- Io::write<Mword>(_orig_reset_vector, Kmem::mmio_remap(Reset_vector_addr));
-}
-
-PUBLIC static
-void
-Platform_control::boot_ap_cpus(Address phys_reset_vector)
-{
- // remember original reset vector
- _orig_reset_vector = Io::read<Mword>(Kmem::mmio_remap(Reset_vector_addr));
-
- // set (temporary) new reset vector
- Io::write<Mword>(phys_reset_vector, Kmem::mmio_remap(Reset_vector_addr));
-
- atexit(reset_orig_reset_vector);
-
- // clocks on other cpu
- Mword r = Io::read<Mword>(Kmem::mmio_remap(Clk_rst_ctrl_clk_cpu_cmplx));
- Io::write<Mword>(r & ~(1 << 9), Kmem::mmio_remap(Clk_rst_ctrl_clk_cpu_cmplx));
- Io::write<Mword>((1 << 13) | (1 << 9) | (1 << 5) | (1 << 1),
- Kmem::mmio_remap(Clk_rst_ctrl_rst_cpu_cmplx_clr));
-
- // kick cpu1
- Io::write<Mword>(0, Kmem::mmio_remap(Unhalt_addr));
-}
-
+++ /dev/null
-// ------------------------------------------------------------------------
-IMPLEMENTATION [arm && tegra2]:
-
-#include "kmem.h"
-#include "mmio_register_block.h"
-
-void __attribute__ ((noreturn))
-platform_reset(void)
-{
- enum { RESET = Mem_layout::Clock_reset_phys_base + 0x4 };
- Mmio_register_block b(Kmem::mmio_remap(RESET));
- b.modify<Mword>(4, 0, 0);
- for (;;)
- ;
-}
+++ /dev/null
-// --------------------------------------------------------------------------
-INTERFACE [arm && tegra2 && mptimer]:
-
-EXTENSION class Timer
-{
-private:
- static Mword interval() { return 249999; }
-};
-
-// --------------------------------------------------------------------------
-INTERFACE [arm && tegra_timer_tmr]:
-
-#include "mmio_register_block.h"
-
-EXTENSION class Timer
-{
-public:
- static unsigned irq() { return 32; };
-
-private:
- static Static_object<Mmio_register_block> _tmr;
-
- struct Reg { enum
- {
- PTV = 0,
- PCR = 4,
- }; };
-};
-
-// --------------------------------------------------------------------------
-IMPLEMENTATION [arm && tegra_timer_tmr]:
-
-#include "kmem.h"
-
-Static_object<Mmio_register_block> Timer::_tmr;
-
-IMPLEMENT
-void Timer::init(Cpu_number cpu)
-{
- if (cpu == Cpu_number::boot_cpu())
- {
- _tmr.construct(Kmem::mmio_remap(Mem_layout::Tmr_phys_base));
- _tmr->write<Mword>( (1 << 31) // enable
- | (1 << 30) // periodic
- | (Config::Scheduler_granularity & 0x1fffffff),
- Reg::PTV);
- }
-}
-
-
-PUBLIC static inline
-void
-Timer::acknowledge()
-{
- _tmr->write<Mword>(1 << 30, Reg::PCR);
-}
-
-IMPLEMENT inline
-void
-Timer::update_one_shot(Unsigned64)
-{}
-
-IMPLEMENT inline NEEDS["config.h", "kip.h"]
-Unsigned64
-Timer::system_clock()
-{
- if (Config::Scheduler_one_shot)
- return 0;
- return Kip::k()->clock;
-}
+++ /dev/null
-INTERFACE [16550 && tegra2]:
-
-EXTENSION class Uart
-{
-public:
- enum {
- Base_rate = 13478400,
- Base_ier_bits = 1 << 6,
-
- Access_shift = 2,
- };
-};
-
-IMPLEMENTATION [16550 && tegra2]:
-
-IMPLEMENT inline NEEDS[Uart::mcr, Uart::ier]
-void Uart::enable_rcv_irq()
-{
- ier(ier() | 1);
-}
projects / l4.git / commitdiff