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[l4.git] / kernel / fiasco / src / kern / arm / bsp / tegra2 / Modules
1 # vim:set ft=make:
2
3 PREPROCESS_PARTS        += tegra2 16550 pic_gic generic_tickless_idle
4 PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_MP)  += mptimer
5 PREPROCESS_PARTS-$(CONFIG_PF_TEGRA_TIMER_TMR) += tegra_timer_tmr
6 RAM_PHYS_BASE           := 0x0
7 INTERFACES_KERNEL       += gic
8 MPCORE_PHYS_BASE        := 0x50040000
9
10 uart_IMPL             += uart-16550 uart-16550-arm-tegra2
11 config_IMPL           += config-arm-tegra2
12 mem_layout_IMPL       += mem_layout-arm-tegra2
13 pic_IMPL              += pic-gic pic-arm-tegra2
14 bootstrap_IMPL        += bootstrap-arm-tegra2
15 timer_IMPL            += $(if $(CONFIG_PF_TEGRA_TIMER_MP),timer-arm-tegra2 timer-arm-mptimer)
16 timer_IMPL            += $(if $(CONFIG_PF_TEGRA_TIMER_TMR),timer-arm-tegra2)
17 timer_tick_IMPL       += $(if $(CONFIG_PF_TEGRA_TIMER_MP),timer_tick-single-vector)
18 timer_tick_IMPL       += $(if $(CONFIG_PF_TEGRA_TIMER_TMR),timer_tick-broadcast)
19 kernel_uart_IMPL      += kernel_uart-arm-tegra2
20 reset_IMPL            += reset-arm-tegra2
21 clock_IMPL            += clock-generic
22 platform_control_IMPL += platform_control-arm-tegra2
23 outer_cache_IMPL      += outer_cache-arm-tegra2