3 * Definitions for H3600 Handheld Computer
5 * Copyright 2001 Compaq Computer Corporation.
7 * Use consistent with the GNU GPL is permitted,
8 * provided that this copyright notice is
9 * preserved in its entirety in all copies and derived works.
11 * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
12 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
13 * FITNESS FOR ANY PARTICULAR PURPOSE.
15 * Author: Andrew Christian
19 #ifndef _INCLUDE_H3600_ASIC_H_
20 #define _INCLUDE_H3600_ASIC_H_
22 //#include <asm-arm/arch-sa1100/h3600.h>
23 #include <arch-sa1100/h3600.h>
26 * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
27 * This file contains machine-specific definitions for the H3800
30 #define GPIO_H3800_ASIC GPIO_GPIO (1)
31 #define GPIO_H3800_AC_IN GPIO_GPIO (12)
32 #define GPIO_H3800_COM_DSR GPIO_GPIO (13)
33 #define GPIO_H3800_MMC_INT GPIO_GPIO (18)
34 #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */
35 #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22)
36 #define GPIO_H3800_CLK_OUT GPIO_GPIO (27)
38 /****************************************************/
40 #define IRQ_GPIO_H3800_ASIC IRQ_GPIO1
41 #define IRQ_GPIO_H3800_AC_IN IRQ_GPIO12
42 #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18
43 #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */
45 /********************* H3800, ASIC #2 ********************/
47 #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT)
48 #define H3800_ASIC2_OFFSET(s,x,y) \
49 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
50 #define H3800_ASIC2_NOFFSET(s,x,n,y) \
51 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
53 #define _H3800_ASIC2_GPIO_Base 0x0000
54 #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */
55 #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
56 #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
57 #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
58 #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */
59 #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */
60 #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */
61 #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
62 #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */
63 #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */
65 #define H3800_ASIC2_GPIODIR H3800_ASIC2_OFFSET( u16, GPIO, Direction )
66 #define H3800_ASIC2_GPIINTTYPE H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
67 #define H3800_ASIC2_GPIINTESEL H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
68 #define H3800_ASIC2_GPIINTALSEL H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
69 #define H3800_ASIC2_GPIINTCLR H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
70 #define H3800_ASIC2_GPIINTFLAG H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
71 #define H3800_ASIC2_GPIOPIOD H3800_ASIC2_OFFSET( u16, GPIO, Data )
72 #define H3800_ASIC2_GPOBFSTAT H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
73 #define H3800_ASIC2_GPIINTSTAT H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
74 #define H3800_ASIC2_GPIOALT H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
76 #define GPIO2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */
77 #define GPIO2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */
78 #define GPIO2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */
79 #define GPIO2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */
80 #define GPIO2_BT_RST (1 << 4) /* Output: Bluetooth reset */
81 #define GPIO2_PEN_IRQ (1 << 5) /* Input : Pen down */
82 #define GPIO2_SD_DETECT (1 << 6) /* Input : SD detect */
83 #define GPIO2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */
84 #define GPIO2_OPT_PCM_RESET (1 << 8) /* Output: Card reset (pin 2 on expansion) */
85 #define GPIO2_OPT_RESET (1 << 9) /* Output: Option pack reset (pin 8 on expansion) */
86 #define GPIO2_USB_DETECT_N (1 << 10) /* Input : */
87 #define GPIO2_SD_CON_SLT (1 << 11) /* Input : */
88 #define GPIO2_OPT_ON (1 << 12) /* Output: Option jacket power */
89 #define GPIO2_OPT_ON_NVRAM (1 << 13) /* Output: Option jacket NVRAM power */
91 #define _H3800_ASIC2_KPIO_Base 0x0200
92 #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */
93 #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
94 #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
95 #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
96 #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */
97 #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */
98 #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */
99 #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
100 #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special (DON'T TRY TO READ!) */
101 #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */
103 #define H3800_ASIC2_KPIODIR H3800_ASIC2_OFFSET( u16, KPIO, Direction )
104 #define H3800_ASIC2_KPIINTTYPE H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
105 #define H3800_ASIC2_KPIINTESEL H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
106 #define H3800_ASIC2_KPIINTALSEL H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
107 #define H3800_ASIC2_KPIINTCLR H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
108 #define H3800_ASIC2_KPIINTFLAG H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
109 #define H3800_ASIC2_KPIOPIOD H3800_ASIC2_OFFSET( u16, KPIO, Data )
110 #define H3800_ASIC2_KPOBFSTAT H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
111 #define H3800_ASIC2_KPIINTSTAT H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
112 #define H3800_ASIC2_KPIOALT H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
114 #define KPIO_SPI_INT (1 << 16)
115 #define KPIO_OWM_INT (1 << 17)
116 #define KPIO_ADC_INT (1 << 18)
117 #define KPIO_UART_0_INT (1 << 19)
118 #define KPIO_UART_1_INT (1 << 20)
119 #define KPIO_TIMER_0_INT (1 << 21)
120 #define KPIO_TIMER_1_INT (1 << 22)
121 #define KPIO_TIMER_2_INT (1 << 23)
123 #define KPIO_RECORD_BTN_N (1 << 0) /* Record button */
124 #define KPIO_KEY_5W1_N (1 << 1) /* Keypad */
125 #define KPIO_KEY_5W2_N (1 << 2) /* */
126 #define KPIO_KEY_5W3_N (1 << 3) /* */
127 #define KPIO_KEY_5W4_N (1 << 4) /* */
128 #define KPIO_KEY_5W5_N (1 << 5) /* */
129 #define KPIO_KEY_LEFT_N (1 << 6) /* */
130 #define KPIO_KEY_RIGHT_N (1 << 7) /* */
131 #define KPIO_KEY_AP1_N (1 << 8) /* Old "Calendar" */
132 #define KPIO_KEY_AP2_N (1 << 9) /* Old "Schedule" */
133 #define KPIO_KEY_AP3_N (1 << 10) /* Old "Q" */
134 #define KPIO_KEY_AP4_N (1 << 11) /* Old "Undo" */
135 #define KPIO_KEY_ALL 0x0fff
137 /* Alternate KPIO functions (set by default) */
138 #define KPIO_ALT_KEY_5W1_N (1 << 1) /* Action key */
139 #define KPIO_ALT_KEY_5W2_N (1 << 2) /* J1 of keypad input */
140 #define KPIO_ALT_KEY_5W3_N (1 << 3) /* J2 of keypad input */
141 #define KPIO_ALT_KEY_5W4_N (1 << 4) /* J3 of keypad input */
142 #define KPIO_ALT_KEY_5W5_N (1 << 5) /* J4 of keypad input */
143 #define KPIO_ALT_KEY_ALL 0x003e
145 #define _H3800_ASIC2_SPI_Base 0x0400
146 #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */
147 #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */
148 #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */
150 #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control )
151 #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data )
152 #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
154 #define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate: valid from 0000 (8kHz) to 1000 (2.048 MHz) */
155 #define SPI_CONTROL_SPE (1 << 4) /* SPI Enable (1:enable, 0:disable) */
156 #define SPI_CONTROL_SPIE (1 << 5) /* SPI Interrupt enable (1:enable, 0:disable) */
157 #define SPI_CONTROL_SEL (1 << 6) /* Chip select: 1:SPI_CS1 enable, 0:SPI_CS0 enable */
158 #define SPI_CONTROL_SEL_CS0 (0 << 6) /* Set CS0 low */
159 #define SPI_CONTROL_SEL_CS1 (1 << 6) /* Set CS0 high */
160 #define SPI_CONTROL_CPOL (1 << 7) /* Clock polarity, 1:SCK high when idle */
162 #define _H3800_ASIC2_PWM_0_Base 0x0600
163 #define _H3800_ASIC2_PWM_1_Base 0x0700
164 #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */
165 #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */
166 #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */
168 #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase )
169 #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
170 #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
172 #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase )
173 #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
174 #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
176 #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base, max = 8 */
177 #define PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */
178 #define PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */
180 #define _H3800_ASIC2_LED_0_Base 0x0800
181 #define _H3800_ASIC2_LED_1_Base 0x0880
182 #define _H3800_ASIC2_LED_2_Base 0x0900
183 #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */
184 #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */
185 #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */
186 #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */
188 #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase )
189 #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
190 #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
191 #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
193 #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase )
194 #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
195 #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
196 #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
198 #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase )
199 #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
200 #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
201 #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
203 #define LEDTBS_MASK 0x0f /* Low 4 bits sets time base, max = 13 */
204 #define LEDTBS_BLINK ( 1 << 4 ) /* Enable blinking */
205 #define LEDTBS_AUTOSTOP ( 1 << 5 )
206 #define LEDTBS_ALWAYS ( 1 << 6 ) /* Enable blink always */
208 #define _H3800_ASIC2_UART_0_Base 0x0A00
209 #define _H3800_ASIC2_UART_1_Base 0x0C00
210 #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */
211 #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */
212 #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */
213 #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */
214 #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */
215 #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */
216 #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */
217 #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */
218 #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */
219 #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */
220 #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */
222 #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive )
223 #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit )
224 #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable )
225 #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify )
226 #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl )
227 #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl )
228 #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus )
229 #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus )
230 #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad )
231 #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL )
232 #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH )
234 #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive )
235 #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit )
236 #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable )
237 #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify )
238 #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl )
239 #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl )
240 #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus )
241 #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus )
242 #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad )
243 #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL )
244 #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH )
246 #define _H3800_ASIC2_TIMER_Base 0x0E00 /* 8254-compatible timers */
247 #define _H3800_ASIC2_TIMER_Counter0 0x0000 /* R/W 8 bits */
248 #define _H3800_ASIC2_TIMER_Counter1 0x0004 /* R/W 8 bits */
249 #define _H3800_ASIC2_TIMER_Counter2 0x0008 /* R/W 8 bits */
250 #define _H3800_ASIC2_TIMER_Control 0x000a /* W 8 bits */
251 #define _H3800_ASIC2_TIMER_Command 0x0010 /* R/W 8 bits */
253 #define H3800_ASIC2_TIMER_Counter0 H3800_ASIC2_OFFSET( u8, TIMER, Counter0 )
254 #define H3800_ASIC2_TIMER_Counter1 H3800_ASIC2_OFFSET( u8, TIMER, Counter1 )
255 #define H3800_ASIC2_TIMER_Counter2 H3800_ASIC2_OFFSET( u8, TIMER, Counter2 )
256 #define H3800_ASIC2_TIMER_Control H3800_ASIC2_OFFSET( u8, TIMER, Control )
257 #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, TIMER, Command )
259 /* These defines are likely incorrect - in particular, TIMER_CNTL_MODE_4 might
261 #define TIMER_CNTL_SELECT(x) (((x)&0x3)<<6) /* Select counter */
262 #define TIMER_CNTL_RW(x) (((x)&0x3)<<4) /* Read/write mode */
263 #define TIMER_CNTL_RW_LATCH TIMER_CNTL_RW(0)
264 #define TIMER_CNTL_RW_LSB_MSB TIMER_CNTL_RW(3) /* LSB first, then MSB */
265 #define TIMER_CNTL_MODE(x) (((x)&0x7)<<1) /* Mode */
266 #define TIMER_CNTL_MODE_0 TIMER_CNTL_MODE(0) /* Supported for 0 & 1 */
267 #define TIMER_CNTL_MODE_2 TIMER_CNTL_MODE(2) /* Supported for all timers */
268 #define TIMER_CNTL_MODE_4 TIMER_CNTL_MODE(4) /* Supported for all timers */
269 #define TIMER_CNTL_BCD ( 1 << 0 ) /* 1=Use BCD counter, 4 decades */
271 #define TIMER_CMD_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */
272 #define TIMER_CMD_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */
273 #define TIMER_CMD_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */
274 #define TIMER_CMD_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */
275 #define TIMER_CMD_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */
276 #define TIMER_CMD_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */
277 #define TIMER_CMD_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */
278 #define TIMER_CMD_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */
280 #define _H3800_ASIC2_CLOCK_Base 0x1000
281 #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */
283 #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
285 #define ASIC2_CLOCK_AUDIO_1 0x01 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
286 #define ASIC2_CLOCK_AUDIO_2 0x02 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
287 #define ASIC2_CLOCK_AUDIO_3 0x04 /* Enable 5.6 MHz clock for 11 kHZ sample rate */
288 #define ASIC2_CLOCK_AUDIO_4 0x08 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
289 #define ASIC2_CLOCK_AUDIO_MASK 0x0f /* Bottom four bits are for audio */
290 #define ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC (CX4) */
291 #define ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI (CX5) */
292 #define ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM (CX6) */
293 #define ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM (CX7) */
294 #define ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) (CX8) */
295 #define ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) (CX9) */
296 #define ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */
297 #define ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */
298 #define ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */
299 #define ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */
300 #define ASIC2_CLOCK_SD_MASK 0x1c00 /* Bits 10 through 12 are for SD */
301 #define ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz (LED,Timer,Interrupt) */
302 #define ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz (ADC,PCM,SPI,PWM,UART,SD,Audio) */
303 #define ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz (SD,Audio) */
304 #define ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */
305 #define ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */
307 #define _H3800_ASIC2_ADC_Base 0x1200
308 #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */
309 #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */
310 #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */
312 #define H3800_ASIC2_ADMUX H3800_ASIC2_OFFSET( u32, ADC, Multiplexer )
313 #define H3800_ASIC2_ADCSR H3800_ASIC2_OFFSET( u8, ADC, ControlStatus )
314 #define H3800_ASIC2_ADCDR H3800_ASIC2_OFFSET( u16, ADC, Data )
316 #define ASIC2_ADMUX(x) ((x)&0x07) /* Low 3 bits sets channel. max = 4 */
317 #define ASIC2_ADMUX_MASK 0x07
318 #define ASIC2_ADMUX_0_LIGHTSENSOR ASIC2_ADMUX(0)
319 #define ASIC2_ADMUX_1_IMIN ASIC2_ADMUX(1)
320 #define ASIC2_ADMUX_2_VS_MBAT ASIC2_ADMUX(2)
321 #define ASIC2_ADMUX_3_TP_X0 ASIC2_ADMUX(3) /* Touchpanel X0 */
322 #define ASIC2_ADMUX_4_TP_Y1 ASIC2_ADMUX(4) /* Touchpanel Y1 */
323 #define ASIC2_ADMUX_CLKEN ( 1 << 3 ) /* Enable clock */
325 #define ASIC2_ADCSR_ADPS(x) ((x)&0x0f) /* Low 4 bits sets prescale, max = 8 */
326 #define ASIC2_ADCSR_FREE_RUN ( 1 << 4 )
327 #define ASIC2_ADCSR_INT_ENABLE ( 1 << 5 )
328 #define ASIC2_ADCSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */
329 #define ASIC2_ADCSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */
332 #define _H3800_ASIC2_INTR_Base 0x1600
333 #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */
334 #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */
335 #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */
337 #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
338 #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
339 #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u16, INTR, TimerSet )
341 #define ASIC2_INTMASK_GLOBAL ( 1 << 0 ) /* Global interrupt mask */
342 //#define ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */
343 //#define ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */
344 #define ASIC2_INTMASK_UART_0 ( 1 << 4 )
345 #define ASIC2_INTMASK_UART_1 ( 1 << 5 )
346 #define ASIC2_INTMASK_TIMER ( 1 << 6 )
347 #define ASIC2_INTMASK_OWM ( 1 << 7 )
349 #define ASIC2_INTCPS_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
350 #define ASIC2_INTCPS_SET ( 1 << 4 ) /* Time base enable */
352 #define _H3800_ASIC2_OWM_Base 0x1800
353 #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */
354 #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */
355 #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */
356 #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */
357 #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */
359 #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command )
360 #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data )
361 #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
362 #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
363 #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
365 #define OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */
366 #define OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */
367 #define OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */
368 #define OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */
370 #define OWM_INT_PD ( 1 << 0 ) /* Presence detect */
371 #define OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */
372 #define OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */
373 #define OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */
374 #define OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */
376 #define OWM_INTEN_EPD ( 1 << 0 ) /* Enable presence detect interrupt */
377 #define OWM_INTEN_IAS ( 1 << 1 ) /* INTR active state */
378 #define OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */
379 #define OWM_INTEN_ETMT ( 1 << 3 ) /* Enable transmit shift register empty interrupt */
380 #define OWM_INTEN_ERBF ( 1 << 4 ) /* Enable receive buffer full interrupt */
382 #define _H3800_ASIC2_FlashCtl_Base 0x1A00
384 /****************************************************/
386 * This ASIC is accesed through ASIC #2, and
387 * mapped into the 1c00 - 1f00 region
390 #define H3800_ASIC1_OFFSET(s,x,y) \
391 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y))))
393 #define _H3800_ASIC1_MMC_Base 0x1c00
395 #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */
396 #define _H3800_ASIC1_MMC_Status 0x04 /* R See below, default 0x0040 */
397 #define _H3800_ASIC1_MMC_ClockRate 0x08 /* R/W 8bit, low 3 bits are clock divisor */
398 #define _H3800_ASIC1_MMC_SPIRegister 0x10 /* R/W 8bit, see below */
399 #define _H3800_ASIC1_MMC_CmdDataCont 0x14 /* R/W 8bit, write to start MMC adapter */
400 #define _H3800_ASIC1_MMC_ResponseTimeout 0x18 /* R/W 8bit, clocks before response timeout */
401 #define _H3800_ASIC1_MMC_ReadTimeout 0x1c /* R/W 16bit, clocks before received data timeout */
402 #define _H3800_ASIC1_MMC_BlockLength 0x20 /* R/W 10bit */
403 #define _H3800_ASIC1_MMC_NumOfBlocks 0x24 /* R/W 16bit, in block mode, number of blocks */
404 #define _H3800_ASIC1_MMC_InterruptMask 0x34 /* R/W 8bit */
405 #define _H3800_ASIC1_MMC_CommandNumber 0x38 /* R/W 6 bits */
406 #define _H3800_ASIC1_MMC_ArgumentH 0x3c /* R/W 16 bits */
407 #define _H3800_ASIC1_MMC_ArgumentL 0x40 /* R/W 16 bits */
408 #define _H3800_ASIC1_MMC_ResFifo 0x44 /* R 8 x 16 bits - contains response FIFO */
409 #define _H3800_ASIC1_MMC_BufferPartFull 0x50 /* R/W 8 bits */
411 #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock )
412 #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status )
413 #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate )
414 #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister )
415 #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont )
416 #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout )
417 #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
418 #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
419 #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
420 #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask )
421 #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber )
422 #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
423 #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
424 #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
425 #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull )
427 #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */
428 #define H3800_ASIC1_MMC_START_CLOCK (1 << 1)
430 #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0)
431 #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1)
432 #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2)
433 #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3)
434 #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */
435 #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5)
436 #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6)
437 #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7)
438 #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */
439 #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */
440 #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */
441 #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */
443 #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */
444 #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */
445 #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */
446 #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */
448 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00
449 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01
450 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02
451 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03
452 #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */
453 #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */
454 #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */
455 #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */
456 #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */
458 #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0)
459 #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1)
460 #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2)
461 #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3)
463 #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0)
465 /********* GPIO **********/
467 #define _H3800_ASIC1_GPIO_Base 0x1e00
469 #define _H3800_ASIC1_GPIO_Mask 0x60 /* R/W 0:don't mask, 1:mask interrupt */
470 #define _H3800_ASIC1_GPIO_Direction 0x64 /* R/W 0:input, 1:output */
471 #define _H3800_ASIC1_GPIO_Out 0x68 /* R/W 0:output low, 1:output high */
472 #define _H3800_ASIC1_GPIO_TriggerType 0x6c /* R/W 0:level, 1:edge */
473 #define _H3800_ASIC1_GPIO_EdgeTrigger 0x70 /* R/W 0:falling, 1:rising */
474 #define _H3800_ASIC1_GPIO_LevelTrigger 0x74 /* R/W 0:low, 1:high level detect */
475 #define _H3800_ASIC1_GPIO_LevelStatus 0x78 /* R/W 0:none, 1:detect */
476 #define _H3800_ASIC1_GPIO_EdgeStatus 0x7c /* R/W 0:none, 1:detect */
477 #define _H3800_ASIC1_GPIO_State 0x80 /* R See masks below (default 0) */
478 #define _H3800_ASIC1_GPIO_Reset 0x84 /* R/W See masks below (default 0x04) */
479 #define _H3800_ASIC1_GPIO_SleepMask 0x88 /* R/W 0:don't mask, 1:mask trigger in sleep mode */
480 #define _H3800_ASIC1_GPIO_SleepDir 0x8c /* R/W direction 0:input, 1:ouput in sleep mode */
481 #define _H3800_ASIC1_GPIO_SleepOut 0x90 /* R/W level 0:low, 1:high in sleep mode */
482 #define _H3800_ASIC1_GPIO_Status 0x94 /* R Pin status */
483 #define _H3800_ASIC1_GPIO_BattFaultDir 0x98 /* R/W direction 0:input, 1:output in batt_fault */
484 #define _H3800_ASIC1_GPIO_BattFaultOut 0x9c /* R/W level 0:low, 1:high in batt_fault */
486 #define H3800_ASIC1_GPIO_MASK H3800_ASIC1_OFFSET( u16, GPIO, Mask )
487 #define H3800_ASIC1_GPIO_DIR H3800_ASIC1_OFFSET( u16, GPIO, Direction )
488 #define H3800_ASIC1_GPIO_OUT H3800_ASIC1_OFFSET( u16, GPIO, Out )
489 #define H3800_ASIC1_GPIO_LEVELTRI H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
490 #define H3800_ASIC1_GPIO_RISING H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
491 #define H3800_ASIC1_GPIO_LEVEL H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
492 #define H3800_ASIC1_GPIO_LEVEL_STATUS H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
493 #define H3800_ASIC1_GPIO_EDGE_STATUS H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
494 #define H3800_ASIC1_GPIO_STATE H3800_ASIC1_OFFSET( u8, GPIO, State )
495 #define H3800_ASIC1_GPIO_RESET H3800_ASIC1_OFFSET( u8, GPIO, Reset )
496 #define H3800_ASIC1_GPIO_SLEEP_MASK H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
497 #define H3800_ASIC1_GPIO_SLEEP_DIR H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
498 #define H3800_ASIC1_GPIO_SLEEP_OUT H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
499 #define H3800_ASIC1_GPIO_STATUS H3800_ASIC1_OFFSET( u16, GPIO, Status )
500 #define H3800_ASIC1_GPIO_BATT_FAULT_DIR H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
501 #define H3800_ASIC1_GPIO_BATT_FAULT_OUT H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
503 #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0)
504 #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1)
505 #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2)
506 #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3)
507 #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4)
508 #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5)
510 #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0)
511 #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1)
512 #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2)
514 /* These are all outputs */
515 #define GPIO1_IR_ON_N (1 << 0) /* Apply power to the IR Module */
516 #define GPIO1_SD_PWR_ON (1 << 1) /* Secure Digital power on */
517 #define GPIO1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */
518 #define GPIO1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */
519 #define GPIO1_CH_TIMER (1 << 4) /* Charger */
520 #define GPIO1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */
521 #define GPIO1_LCD_ON (1 << 6) /* Enables LCD_3V */
522 #define GPIO1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */
523 #define GPIO1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */
524 #define GPIO1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */
525 #define GPIO1_FL_PWR_ON (1 << 10) /* Frontlight power on */
526 #define GPIO1_BT_PWR_ON (1 << 11) /* Bluetooth power on */
527 #define GPIO1_SPK_ON (1 << 12) /* Built-in speaker on */
528 #define GPIO1_EAR_ON_N (1 << 13) /* Headphone jack on */
529 #define GPIO1_AUD_PWR_ON (1 << 14) /* All audio power */
531 /* Write enable for the flash */
533 #define _H3800_ASIC2_FlashWP_Base 0x1f00
534 #define _H3800_ASIC2_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */
535 #define H3800_ASIC2_FlashWP_VPP_ON H3800_ASIC2_OFFSET( u8, FlashWP, VPP_ON )
537 /****************************************************/
538 /* H3900, ASIC #3, replaces ASIC #1
539 * This ASIC is at CS5# + 0x00000000
541 #ifdef CONFIG_MACH_H3900
543 #define H3900_ASIC3_OFFSET(s,x,y) \
544 (*((volatile s *) (H3900_ASIC3_VIRT + _H3900_ASIC3_ ## x ## _Base + (_H3900_ASIC3_ ## x ## _ ## y))))
546 #define _H3900_ASIC3_GPIO_A_Base 0x0000
547 #define _H3900_ASIC3_GPIO_B_Base 0x0100
549 #define _H3900_ASIC3_GPIO_B_Mask 0x00 /* R/W 0:don't mask, 1:mask interrupt */
550 #define _H3900_ASIC3_GPIO_B_Direction 0x04 /* R/W 0:input, 1:output */
551 #define _H3900_ASIC3_GPIO_B_Out 0x08 /* R/W 0:output low, 1:output high */
552 #define _H3900_ASIC3_GPIO_B_TriggerType 0x0c /* R/W 0:level, 1:edge */
553 #define _H3900_ASIC3_GPIO_B_EdgeTrigger 0x10 /* R/W 0:falling, 1:rising */
554 #define _H3900_ASIC3_GPIO_B_LevelTrigger 0x14 /* R/W 0:low, 1:high level detect */
555 #define _H3900_ASIC3_GPIO_B_SleepMask 0x18 /* R/W 0:don't mask, 1:mask trigger in sleep mode */
556 #define _H3900_ASIC3_GPIO_B_SleepOut 0x1c /* R/W level 0:low, 1:high in sleep mode */
557 #define _H3900_ASIC3_GPIO_B_BattFaultOut 0x20 /* R/W level 0:low, 1:high in batt_fault */
558 #define _H3900_ASIC3_GPIO_B_IntStatus 0x24 /* R/W 0:none, 1:detect */
560 #define _H3900_ASIC3_GPIO_B_SleepConf 0x2c /* R/W bit 1: autosleep 0: disable gposlpout in normal mode, enable gposlpout in sleep mode */
561 #define _H3900_ASIC3_GPIO_B_Status 0x30 /* R Pin status */
563 #define H3900_ASIC3_GPIO_B_MASK H3900_ASIC3_OFFSET( u16, GPIO_B, Mask )
564 #define H3900_ASIC3_GPIO_B_DIR H3900_ASIC3_OFFSET( u16, GPIO_B, Direction )
565 #define H3900_ASIC3_GPIO_B_OUT H3900_ASIC3_OFFSET( u16, GPIO_B, Out )
566 #define H3900_ASIC3_GPIO_B_LEVELTRI H3900_ASIC3_OFFSET( u16, GPIO_B, TriggerType )
567 #define H3900_ASIC3_GPIO_B_RISING H3900_ASIC3_OFFSET( u16, GPIO_B, EdgeTrigger )
568 #define H3900_ASIC3_GPIO_B_LEVEL H3900_ASIC3_OFFSET( u16, GPIO_B, LevelTrigger )
569 #define H3900_ASIC3_GPIO_B_SLEEP_MASK H3900_ASIC3_OFFSET( u16, GPIO_B, SleepMask )
570 #define H3900_ASIC3_GPIO_B_SLEEP_OUT H3900_ASIC3_OFFSET( u16, GPIO_B, SleepOut )
571 #define H3900_ASIC3_GPIO_B_BATT_FAULT_OUT H3900_ASIC3_OFFSET( u16, GPIO_B, BattFaultOut )
572 #define H3900_ASIC3_GPIO_B_INT_STATUS H3900_ASIC3_OFFSET( u16, GPIO_B, IntStatus )
573 #define H3900_ASIC3_GPIO_B_SLEEP_CONF H3900_ASIC3_OFFSET( u16, GPIO_B, SleepConf )
574 #define H3900_ASIC3_GPIO_B_STATUS H3900_ASIC3_OFFSET( u16, GPIO_B, Status )
576 /* these gpio's are on GPIO_B */
578 #define GPIO3_IR_ON_N (1 << 0) /* Apply power to the IR Module */
579 #define GPIO3_LCD_9V_ON (1 << 1)
580 #define GPIO3_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */
581 #define GPIO3_LCD_NV_ON (1 << 3)
582 #define GPIO3_CH_TIMER (1 << 4) /* Charger */
583 #define GPIO3_LCD_5V_ON (1 << 5) /* Enables LCD_5V */
584 #define GPIO3_LCD_ON (1 << 6) /* Enables LCD_3V */
585 #define GPIO3_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */
586 // 8 is not connected
587 #define GPIO3_CIR_CTL_PWR_ON (1 << 9)
588 #define GPIO3_AUD_RESET (1 << 10)
589 #define GPIO3_BT_PWR_ON (1 << 11) /* Bluetooth power on */
590 #define GPIO3_SPK_ON (1 << 12) /* Built-in speaker on */
591 #define GPIO3_FL_PWR_ON (1 << 13) /* Frontlight power on */
592 #define GPIO3_AUD_PWR_ON (1 << 14) /* All audio power */
594 #define _H3900_ASIC3_GPIO_B_Base 0x0100
595 #define _H3900_ASIC3_GPIO_C_Base 0x0200
596 #define _H3900_ASIC3_GPIO_D_Base 0x0300
597 #define _H3900_ASIC3_CLOCK_Base 0x0A00
598 #define _H3900_ASIC3_INTR_Base 0x0B00
599 #define _H3900_ASIC3_SDHWCTRL_Base 0x0E00
600 #define _H3900_ASIC3_HWPROTECT_Base 0x1000
601 #define _H3900_ASIC3_EXTCF_Base 0x1100
603 #define ASIC3GPIO_INIT_DIR 0xFFFF // initial status, sleep direction
604 #define ASIC3GPIO_INIT_OUT 0x8200 // Strain 2001.12.15
605 #define ASIC3GPIO_BATFALT_OUT 0x8000
606 #define ASIC3GPIO_SLEEP_OUT 0x8000
607 #define ASIC3CLOCK_INIT 0x0
611 #endif /* _INCLUDE_H3600_GPIO_H_ */
projects / l4.git / blob