8 class Vm_svm : public Vm
11 static void resume_vm_svm(Mword phys_vmcb, Mword *regs)
12 asm("resume_vm_svm") __attribute__((__regparm__(3)));
13 Unsigned8 _asid[Config::Max_num_cpus];
14 Unsigned32 _asid_generation[Config::Max_num_cpus];
23 // ------------------------------------------------------------------------
24 INTERFACE [svm && debug]:
26 EXTENSION class Vm_svm
29 struct Log_vm_svm_exit
31 Mword exitcode, exitinfo1, exitinfo2, rip;
34 static unsigned log_fmt_svm(Tb_entry *, int max, char *buf) asm ("__fmt_vm_svm_exit");
37 // ------------------------------------------------------------------------
41 #include "mem_space.h"
45 #include "thread.h" // XXX: circular dep, move this out here!
46 #include "thread_state.h" // XXX: circular dep, move this out here!
49 // ------------------------------------------------------------------------
50 IMPLEMENTATION [svm && ia32]:
54 PRIVATE inline NEEDS["virt.h"]
56 Vm_svm::get_vm_cr3(Vmcb *)
58 // When running in 32bit mode we already return the page-table of our Vm
59 // object, whether we're running with shadow or nested paging
60 return mem_space()->phys_dir();
63 //----------------------------------------------------------------------------
64 IMPLEMENTATION [svm && amd64]:
68 PRIVATE inline NEEDS["virt.h"]
70 Vm_svm::get_vm_cr3(Vmcb *v)
72 // When we have nested paging, we just return the 4lvl host page-table of
75 return mem_space()->phys_dir();
77 // When running with shadow paging and the guest is running in long mode
78 // and has paging enabled, we can just return the 4lvl page table of our
80 if ( (v->state_save_area.efer & EFER_LME)
81 && (v->state_save_area.cr0 & CR0_PG))
82 return mem_space()->phys_dir();
84 // Now it's getting tricky when running with shadow paging.
85 // We need to obey the following rules:
86 // - When the guest is not running in 64bit mode the CR3 one can set for
87 // the page-table must be below 4G physical memory (i.e. bit 32-63 must
88 // be zero). This is unfortunate when the host has memory above 4G as
89 // Fiasco gets its memory from the end of physical memory, i.e.
90 // page-table memory is above 4G.
91 // - We need an appropriate page-table format for 32bit!
92 // That means either a 2lvl page-table or a 3lvl PAE one. That would
93 // require to maintain two page-tables for the guest, one for 32bit
94 // mode execution and one for 64 bit execution. It is needed either for
95 // the transition from real to long-mode via protected mode or for
97 // There's one trick to avoid having two PTs: 4lvl-PTs and 3lvl-PAE-PTs
98 // have much in common so that it's possible to just take the the PDPE
99 // one of the host as the 3lvl-PAE-PT for the guest. Well, not quite.
100 // The problem is that SVM checks that MBZ bits in the PAE-PT entries
101 // are really 0 as written in the spec. Now the 4lvl PT contains rights
102 // bits there, so that this type of PT is refused and does not work on
104 // So why is the code still here? Well, QEmu isn't so picky about the
105 // bits in the PDPE and it thus works there...
106 Address vm_cr3 = mem_space()->dir()->walk(Virt_addr(0), 0).e->addr();
107 if (EXPECT_FALSE(!vm_cr3))
109 // force allocation of new secondary page-table level
110 mem_space()->dir()->alloc_cast<Mem_space_q_alloc>()
111 ->walk(Virt_addr(0), 1, Mem_space_q_alloc(ram_quota(),
112 Mapped_allocator::allocator()));
113 vm_cr3 = mem_space()->dir()->walk(Virt_addr(0), 0).e->addr();
116 if (EXPECT_FALSE(vm_cr3 >= 1UL << 32))
118 WARN("svm: Host page-table not under 4G, sorry.\n");
125 //----------------------------------------------------------------------------
126 IMPLEMENTATION [svm]:
132 return _asid[current_cpu()];
137 Vm_svm::asid (Unsigned8 asid)
139 _asid[current_cpu()] = asid;
144 Vm_svm::asid_generation ()
146 return _asid_generation[current_cpu()];
151 Vm_svm::asid_generation (Unsigned32 generation)
153 _asid_generation[current_cpu()] = generation;
157 Vm_svm::Vm_svm(Ram_quota *q)
160 memset(_asid, 0, sizeof(_asid));
161 memset(_asid_generation, 0, sizeof(_asid_generation));
166 Vm_svm::operator new (size_t size, void *p)
169 assert (size == sizeof (Vm_svm));
175 Vm_svm::operator delete (void *ptr)
177 Vm_svm *t = reinterpret_cast<Vm_svm*>(ptr);
178 allocator<Vm_svm>()->q_free(t->ram_quota(), ptr);
184 // - force fpu ownership
185 // - debug registers not covered by VMCB
189 Vm_svm::copy_state_save_area(Vmcb *dest, Vmcb *src)
191 Vmcb_state_save_area *d = &dest->state_save_area;
192 Vmcb_state_save_area *s = &src->state_save_area;
194 d->es_sel = s->es_sel;
195 d->es_attrib = s->es_attrib;
196 d->es_limit = s->es_limit;
197 d->es_base = s->es_base;
199 d->cs_sel = s->cs_sel;
200 d->cs_attrib = s->cs_attrib;
201 d->cs_limit = s->cs_limit;
202 d->cs_base = s->cs_base;
204 d->ss_sel = s->ss_sel;
205 d->ss_attrib = s->ss_attrib;
206 d->ss_limit = s->ss_limit;
207 d->ss_base = s->ss_base;
209 d->ds_sel = s->ds_sel;
210 d->ds_attrib = s->ds_attrib;
211 d->ds_limit = s->ds_limit;
212 d->ds_base = s->ds_base;
214 d->fs_sel = s->fs_sel;
215 d->fs_attrib = s->fs_attrib;
216 d->fs_limit = s->fs_limit;
217 d->fs_base = s->fs_base;
219 d->gs_sel = s->gs_sel;
220 d->gs_attrib = s->gs_attrib;
221 d->gs_limit = s->gs_limit;
222 d->gs_base = s->gs_base;
224 d->gdtr_sel = s->gdtr_sel;
225 d->gdtr_attrib = s->gdtr_attrib;
226 d->gdtr_limit = s->gdtr_limit;
227 d->gdtr_base = s->gdtr_base;
229 d->ldtr_sel = s->ldtr_sel;
230 d->ldtr_attrib = s->ldtr_attrib;
231 d->ldtr_limit = s->ldtr_limit;
232 d->ldtr_base = s->ldtr_base;
234 d->idtr_sel = s->idtr_sel;
235 d->idtr_attrib = s->idtr_attrib;
236 d->idtr_limit = s->idtr_limit;
237 d->idtr_base = s->idtr_base;
239 d->tr_sel = s->tr_sel;
240 d->tr_attrib = s->tr_attrib;
241 d->tr_limit = s->tr_limit;
242 d->tr_base = s->tr_base;
252 d->rflags = s->rflags;
261 d->sfmask = s->sfmask;
262 d->kernelgsbase = s->kernelgsbase;
263 d->sysenter_cs = s->sysenter_cs;
264 d->sysenter_esp = s->sysenter_esp;
265 d->sysenter_eip = s->sysenter_eip;
269 d->dbgctl = s->dbgctl;
270 d->br_from = s->br_from;
272 d->lastexcpfrom = s->lastexcpfrom;
273 d->last_excpto = s->last_excpto;
279 Vm_svm::copy_control_area(Vmcb *dest, Vmcb *src)
281 Vmcb_control_area *d = &dest->control_area;
282 Vmcb_control_area *s = &src->control_area;
284 d->intercept_rd_crX = s->intercept_rd_crX;
285 d->intercept_wr_crX = s->intercept_wr_crX;
287 d->intercept_rd_drX = s->intercept_rd_drX;
288 d->intercept_wr_drX = s->intercept_wr_drX;
290 d->intercept_exceptions = s->intercept_exceptions;
292 d->intercept_instruction0 = s->intercept_instruction0;
293 d->intercept_instruction1 = s->intercept_instruction1;
295 // skip iopm_base_pa and msrpm_base_pa
297 d->tsc_offset = s->tsc_offset;
298 d->guest_asid_tlb_ctl = s->guest_asid_tlb_ctl;
299 d->interrupt_ctl = s->interrupt_ctl;
300 d->interrupt_shadow = s->interrupt_shadow;
301 d->exitcode = s->exitcode;
302 d->exitinfo1 = s->exitinfo1;
303 d->exitinfo2 = s->exitinfo2;
304 d->exitintinfo = s->exitintinfo;
305 d->np_enable = s->np_enable;
307 d->eventinj = s->eventinj;
309 d->lbr_virtualization_enable = s->lbr_virtualization_enable;
313 /* skip anything that does not change */
316 Vm_svm::copy_control_area_back(Vmcb *dest, Vmcb *src)
318 Vmcb_control_area *d = &dest->control_area;
319 Vmcb_control_area *s = &src->control_area;
321 d->interrupt_ctl = s->interrupt_ctl;
322 d->interrupt_shadow = s->interrupt_shadow;
324 d->exitcode = s->exitcode;
325 d->exitinfo1 = s->exitinfo1;
326 d->exitinfo2 = s->exitinfo2;
327 d->exitintinfo = s->exitintinfo;
329 d->eventinj = s->eventinj;
332 /** \brief Choose an ASID for this Vm.
334 * Choose an ASID for this Vm. The ASID provided by userspace is ignored
335 * instead the kernel picks one.
336 * Userspace uses the flush-bit to receive a new ASID for this Vm.
337 * All ASIDs are flushed as soon as the kernel runs out of ASIDs.
339 * @param vmcb_s external VMCB provided by userspace
340 * @param kernel_vmcb_s our VMCB
345 Vm_svm::configure_asid (Vmcb *vmcb_s, Vmcb *kernel_vmcb_s)
347 assert (cpu_lock.test());
349 Svm &s = Svm::cpus.cpu(current_cpu());
351 if (// vmm requests flush
352 ((vmcb_s->control_area.guest_asid_tlb_ctl >> 32) & 1) == 1 ||
353 // our asid is not valid or expired
354 !(s.asid_valid(asid(), asid_generation())))
357 asid_generation(s.global_asid_generation());
360 assert(s.asid_valid(asid(), asid_generation()));
362 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = asid();
363 if (s.flush_all_asids())
365 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
366 s.flush_all_asids(false);
369 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = 1;
370 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
376 Vm_svm::sys_vm_run(Syscall_frame *f, Utcb *utcb)
379 Unsigned64 orig_cr3, orig_ncr3;
381 assert (cpu_lock.test());
383 /* these 4 must not use ldt entries */
384 assert (!(Cpu::get_cs() & (1 << 2)));
385 assert (!(Cpu::get_ss() & (1 << 2)));
386 assert (!(Cpu::get_ds() & (1 << 2)));
387 assert (!(Cpu::get_es() & (1 << 2)));
389 Svm &s = Svm::cpus.cpu(current_cpu());
391 L4_msg_tag const &tag = f->tag();
393 if (EXPECT_FALSE(!s.svm_enabled()))
395 WARN("svm: not supported/enabled\n");
396 return commit_result(-L4_err::EInval);
399 if (EXPECT_FALSE(tag.words() < 2 + Svm::Gpregs_words))
401 WARN("svm: Invalid message length\n");
402 return commit_result(-L4_err::EInval);
405 L4_snd_item_iter vmcb_item(utcb, tag.words());
407 if (EXPECT_FALSE(!tag.items() || !vmcb_item.next()))
408 return commit_result(-L4_err::EInval);
410 L4_fpage vmcb_fpage(vmcb_item.get()->d);
412 if (EXPECT_FALSE(!vmcb_fpage.is_mempage()))
414 WARN("svm: Fpage invalid\n");
415 return commit_error(utcb, L4_error::Overflow);
418 if (EXPECT_FALSE(vmcb_fpage.order() < 12))
419 return commit_result(-L4_err::EInval);
421 Vmcb *vmcb_s = (Vmcb *)(Virt_addr(vmcb_fpage.mem_address()).value());
422 Vmcb *kernel_vmcb_s = s.kernel_vmcb();
424 if (EXPECT_FALSE(vmcb_s->np_enabled() && !s.has_npt()))
426 WARN("svm: No NPT available\n");
427 return commit_result(-L4_err::EInval);
430 Address vm_cr3 = get_vm_cr3(vmcb_s);
431 // can only fail on 64bit, will be optimized away on 32bit
432 if (EXPECT_FALSE(is_64bit() && !vm_cr3))
433 return commit_result(-L4_err::ENomem);
435 Mem_space::Phys_addr phys_vmcb;
436 Mem_space::Size size;
438 unsigned int page_attribs;
440 Mem_space *const curr_mem_space = current()->space()->mem_space();
441 resident = curr_mem_space->v_lookup(Virt_addr(vmcb_s), &phys_vmcb, &size, &page_attribs);
445 WARN("svm: VMCB invalid\n");
446 return commit_result(-L4_err::EInval);
449 // currently only support for nested pagetables
450 // if shadow page tables are to be allowed then cr0
451 // needs further scrutiny and cr3 must not be accessible
452 if((vmcb_s->control_area.np_enable & 1) != 1)
453 return commit_result(-L4_err::EInval);
456 // neither EFER.LME nor EFER.LMA must be set
457 if (EXPECT_FALSE(!is_64bit()
458 && (vmcb_s->state_save_area.efer & (EFER_LME | EFER_LMA))))
460 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
461 return commit_result(-L4_err::EInval);
464 // EFER.SVME must be set
465 if (!(vmcb_s->state_save_area.efer & 0x1000))
467 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
468 return commit_result(-L4_err::EInval);
470 // allow PAE in combination with NPT
472 // CR4.PAE must be clear
473 if(vmcb_s->state_save_area.cr4 & 0x20)
474 return commit_result(-L4_err::EInval);
478 // This generates a circular dep between thread<->task, this cries for a
479 // new abstraction...
480 if (!(current()->state() & Thread_fpu_owner))
482 if (!current_thread()->switchin_fpu())
484 WARN("svm: switchin_fpu failed\n");
485 return commit_result(-L4_err::EInval);
489 #if 0 //should never happen
490 host_cr0 = Cpu::get_cr0();
491 // the VMM does not currently own the fpu but wants to
492 // make it available for the guest. This may happen
493 // if it was descheduled between activating the fpu and
494 // executing the vm_run operation
495 if (!(vmcb_s->state_save_area.cr0 & 0x8) && (host_cr0 & 0x8))
497 WARN("svm: FPU TS\n");
498 return commit_result(-L4_err::EInval);
502 // increment our refcount, and drop it at the end automatically
503 Ref_ptr<Vm_svm> pin_myself(this);
507 orig_cr3 = vmcb_s->state_save_area.cr3;
508 orig_ncr3 = vmcb_s->control_area.n_cr3;
510 copy_control_area(kernel_vmcb_s, vmcb_s);
511 copy_state_save_area(kernel_vmcb_s, vmcb_s);
513 if (EXPECT_FALSE(is_64bit() && !kernel_vmcb_s->np_enabled()
514 && (kernel_vmcb_s->state_save_area.cr0 & CR0_PG)
515 && !(kernel_vmcb_s->state_save_area.cr4 & CR4_PAE)))
517 WARN("svm: No 32bit shadow page-tables on AMD64, use PAE!\n");
518 return commit_result(-L4_err::EInval);
521 // set MCE according to host
522 kernel_vmcb_s->state_save_area.cr4 |= Cpu::get_cr4() & CR4_MCE;
524 // allow w access to cr0, cr2, cr3
525 // allow r access to cr0, cr2, cr3, cr4
526 // to do: check if enabling PAE in cr4 needs to be controlled
528 // allow r/w access to dr[0-7]
529 kernel_vmcb_s->control_area.intercept_rd_drX |= 0xff00;
530 kernel_vmcb_s->control_area.intercept_wr_drX |= 0xff00;
533 // intercept exception vectors 0-31
534 kernel_vmcb_s->control_area.intercept_exceptions = 0xffffffff;
537 // enable iopm and msrpm
538 kernel_vmcb_s->control_area.intercept_instruction0 |= 0x18000000;
539 // intercept FERR_FREEZE and shutdown events
540 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xc0000000;
541 // intercept INTR/NMI/SMI/INIT
542 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xf;
544 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 22);
546 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 24);
547 // intercept task switch
548 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 29);
549 // intercept shutdown
550 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 31);
551 // intercept MONITOR/MWAIT
552 kernel_vmcb_s->control_area.intercept_instruction1 |= (1 << 10) | (1 << 11);
554 // intercept virtualization related instructions
555 // vmrun interception is required by the hardware
556 kernel_vmcb_s->control_area.intercept_instruction1 |= 0xff;
558 Mword kernel_vmcb_pa = s.kernel_vmcb_pa();
559 Unsigned64 iopm_base_pa = s.iopm_base_pa();
560 Unsigned64 msrpm_base_pa = s.msrpm_base_pa();
562 kernel_vmcb_s->control_area.iopm_base_pa = iopm_base_pa;
563 kernel_vmcb_s->control_area.msrpm_base_pa = msrpm_base_pa;
565 configure_asid(vmcb_s, kernel_vmcb_s);
567 // 7:0 V_TPR, 8 V_IRQ, 15:9 reserved SBZ,
568 // 19:16 V_INTR_PRIO, 20 V_IGN_TPR, 23:21 reserved SBZ
569 // 24 V_INTR_MASKING 31:25 reserved SBZ
570 // 39:32 V_INTR_VECTOR, 63:40 reserved SBZ
572 kernel_vmcb_s->control_area.interrupt_ctl = 0x10f0000;
574 // enable IRQ masking virtualization
575 kernel_vmcb_s->control_area.interrupt_ctl |= 0x01000000;
578 // 0 INTERRUPT_SHADOW, 31:1 reserved SBZ
579 // 63:32 reserved SBZ
580 kernel_vmcb_s->control_area.interrupt_shadow = 0;
583 kernel_vmcb_s->control_area.exitcode = 0;
584 kernel_vmcb_s->control_area.exitinfo1 = 0;
585 kernel_vmcb_s->control_area.exitinfo2 = 0;
586 kernel_vmcb_s->control_area.exitintinfo = 0;
589 // 0/1 NP_ENABLE, 31:1 reserved SBZ
590 kernel_vmcb_s->control_area.np_enable = 1;
592 // 31 VALID, EVENTINJ
593 kernel_vmcb_s->control_area.eventinj = 0;
597 kernel_vmcb_s->control_area.n_cr3 = vm_cr3;
599 if (!kernel_vmcb_s->np_enabled())
601 // to do: check that the vmtask has the
602 // VM property set, i.e. does not contain mappings
603 // to the fiasco kernel regions or runs with PL 3
605 // printf("nested paging disabled, use n_cr3 as cr3\n");
606 kernel_vmcb_s->state_save_area.cr3 = vm_cr3;
608 // intercept accesses to cr0, cr3 and cr4
609 kernel_vmcb_s->control_area.intercept_rd_crX = 0xfff9;
610 kernel_vmcb_s->control_area.intercept_wr_crX = 0xfff9;
614 kernel_vmcb_s->control_area.lbr_virtualization_enable = 0;
619 // - initialize VM_HSAVE_PA (done)
620 // - supply trusted msrpm_base_pa and iopm_base_pa (done)
621 // - save host state not covered by VMRUN/VMEXIT (ldt, some segments etc) (done)
622 // - disable interupts (done)
623 // - trigger interecepted device and timer interrupts (done, not necessary)
624 // - check host CR0.TS (floating point registers) (done)
626 Unsigned64 sysenter_cs, sysenter_eip, sysenter_esp;
631 sysenter_cs = Cpu::rdmsr(MSR_SYSENTER_CS);
632 sysenter_eip = Cpu::rdmsr(MSR_SYSENTER_EIP);
633 sysenter_esp = Cpu::rdmsr(MSR_SYSENTER_ESP);
638 ldtr = Cpu::get_ldt();
642 tr_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
645 // to do: check if the nested page table walker looks
646 // into the TLB. if so, global pages have to be disabled in
648 cr4 = Cpu::get_cr4();
651 // disable support for global pages as the vm task has
652 // a divergent upper memory region from the regular tasks
653 Cpu::set_cr4(cr4 & ~CR4_PGE);
656 resume_vm_svm(kernel_vmcb_pa, &utcb->values[2]);
664 Cpu::wrmsr(sysenter_cs, MSR_SYSENTER_CS);
665 Cpu::wrmsr(sysenter_eip, MSR_SYSENTER_EIP);
666 Cpu::wrmsr(sysenter_esp, MSR_SYSENTER_ESP);
675 tss_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
676 tss_entry.access &= 0xfd;
677 (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8] = tss_entry;
679 Cpu::set_tr(tr); // TODO move under stgi in asm
681 copy_state_save_area(vmcb_s, kernel_vmcb_s);
682 copy_control_area_back(vmcb_s, kernel_vmcb_s);
684 if (!(vmcb_s->np_enabled()))
685 vmcb_s->state_save_area.cr3 = orig_cr3;
687 vmcb_s->control_area.n_cr3 = orig_ncr3;
689 LOG_TRACE("VM-SVM", "svm", current(), __fmt_vm_svm_exit,
690 Log_vm_svm_exit *l = tbe->payload<Log_vm_svm_exit>();
691 l->exitcode = vmcb_s->control_area.exitcode;
692 l->exitinfo1 = vmcb_s->control_area.exitinfo1;
693 l->exitinfo2 = vmcb_s->control_area.exitinfo2;
694 l->rip = vmcb_s->state_save_area.rip;
697 return commit_result(L4_error::None);
702 Vm_svm::invoke(L4_obj_ref obj, Mword rights, Syscall_frame *f, Utcb *utcb)
704 vm_invoke<Vm_svm>(obj, rights, f, utcb);
707 // ------------------------------------------------------------------------
708 IMPLEMENTATION [svm && debug]:
712 Vm_svm::log_fmt_svm(Tb_entry *e, int max, char *buf)
714 Log_vm_svm_exit *l = e->payload<Log_vm_svm_exit>();
715 return snprintf(buf, max, "ec=%lx ei1=%08lx ei2=%08lx rip=%08lx",
716 l->exitcode, l->exitinfo1, l->exitinfo2, l->rip);