2 * (c) 2010 Alexander Warg <warg@os.inf.tu-dresden.de>
3 * economic rights: Technische Universität Dresden (Germany)
5 * This file is part of TUD:OS and distributed under the terms of the
6 * GNU General Public License 2.
7 * Please see the COPYING-GPL-2 file for details.
10 #include "app_model.h"
13 #include <l4/re/error_helper>
14 #include <l4/re/util/env_ns>
15 #include <l4/util/bitops.h>
21 App_model::alloc_ds(unsigned long size) const
23 Dataspace mem = chkcap(L4Re::Util::cap_alloc.alloc<L4Re::Dataspace>(),
24 "allocate capability");
25 L4::Cap<L4Re::Mem_alloc> _ma(prog_info()->mem_alloc.raw & L4_FPAGE_ADDR_MASK);
26 chksys(_ma->alloc(size, mem.get()), "allocate writabel program segment");
30 App_model::Const_dataspace
31 App_model::open_file(char const *name)
34 L4Re::Util::Env_ns ens;
36 L4::Cap<L4Re::Dataspace> f;
38 f = chkcap(ens.query<L4Re::Dataspace>(name), name, 0);
44 App_model::prog_attach_ds(l4_addr_t addr, unsigned long size,
45 Const_dataspace ds, unsigned long offset,
46 unsigned flags, char const *what)
48 _stack.add(addr, size, _task->rm(), ds.get(), offset, flags, 0, what);
52 App_model::prog_reserve_area(l4_addr_t *start, unsigned long size,
53 unsigned flags, unsigned char align)
55 return _task->rm()->reserve_area(start, size, flags, align);
60 App_model::copy_ds(Dataspace dst, unsigned long dst_offs,
61 Const_dataspace src, unsigned long src_offs,
64 if (dst->copy_in(dst_offs, src.get(), src_offs, size) < 0)
66 L4::Cap<L4Re::Rm> r = L4Re::Env::env()->rm();
67 L4Re::Rm::Auto_region<char const *> data;
68 chksys(r->attach(&data, size, L4Re::Rm::Search_addr | L4Re::Rm::Read_only,
69 src.get(), src_offs));
72 //memcpy(paddr + page_offs, data.get() + page_offs, fsz);
78 App_model::local_attach_ds(Const_dataspace ds, unsigned long size,
79 unsigned long offset) const
81 L4::Cap<L4Re::Rm> rm = L4Re::Env::env()->rm();
82 l4_addr_t pg_offset = l4_trunc_page(offset);
83 l4_addr_t in_pg_offset = offset - pg_offset;
84 unsigned long pg_size = l4_round_page(size + in_pg_offset);
86 chksys(rm->attach(&vaddr, pg_size,
87 L4Re::Rm::Search_addr | L4Re::Rm::Read_only,
88 ds.get(), pg_offset), "attach temporary VMA");
89 return vaddr + in_pg_offset;
93 App_model::local_detach_ds(l4_addr_t addr, unsigned long /*size*/) const
95 L4::Cap<L4Re::Rm> rm = L4Re::Env::env()->rm();
96 l4_addr_t pg_addr = l4_trunc_page(addr);
97 chksys(rm->detach(pg_addr, 0), "detach temporary VMA");
101 App_model::App_model()
104 // set default values for utcb area, values may be changed by loader
105 _info.utcbs_start = Utcb_area_start;
106 _info.utcbs_log2size = l4util_log2(Default_max_threads * L4_UTCB_OFFSET);
108 // set default values for the application stack
109 _info.kip = Kip_address;
114 App_model::alloc_app_stack()
116 L4Re::Util::Ref_cap<L4Re::Dataspace>::Cap stack
117 = chkcap(L4Re::Util::cap_alloc.alloc<L4Re::Dataspace>(),
118 "allocate stack capability");
119 L4::Cap<L4Re::Mem_alloc> _ma(prog_info()->mem_alloc.raw & L4_FPAGE_ADDR_MASK);
120 chksys(_ma->alloc(_stack.stack_size(), stack.get()),
123 _stack.set_stack(stack, _stack.stack_size());
125 return stack.release();
129 App_model::init_prog()
136 _info.mem_alloc = _ma.fpage();
137 _info.names = _ns.fpage();
138 _info.log = _log.fpage();
139 _info.factory = _factory.fpage();
140 _info.scheduler = _sched.fpage();
144 _info.ldr_flags = parser.ldr_flags.data;
145 _info.l4re_dbg = parser.l4re_dbg.data;
147 if (parser.cpu_affinity.data != ~0UL || parser.base_prio.data != Default_base_prio
148 || parser.max_prio.data != Default_max_prio)
150 info.printf(" base_prio = 0x%x max_prio = 0x%x\n",
151 parser.base_prio.data, parser.max_prio.data);
152 _task->_sched.set_prio(parser.base_prio.data, parser.max_prio.data);
153 _task->_sched.restrict_cpus(parser.cpu_affinity.data);
154 Gate_alloc::alloc(&_task->_sched);
155 _info.scheduler = _task->_sched.obj_cap().fpage();
156 scheduler_if = &_task->_sched;
159 info.printf("loading '%s'\n", argv.a0);
163 App_model::get_task_caps(L4::Cap<L4::Factory> *factory,
164 L4::Cap<L4::Task> *task,
165 L4::Cap<L4::Thread> *thread)
167 prog_info()->rm = _task->rm().fpage();
168 prog_info()->parent = _task->obj_cap().fpage();
169 Dbg(Dbg::Info).printf("parent cap is %lx\n", prog_info()->parent.raw);
170 *task = _task->task_cap();
171 *thread = _task->thread_cap();
172 *factory = L4::Cap<L4::Factory>(prog_info()->factory.raw & L4_FPAGE_ADDR_MASK);