1 // ---------------------------------------------------------------------
2 INTERFACE [arm && imx]:
13 Multi_irq_pending = 0,
19 INTCTL = Kmem::Pic_map_base + 0x00,
20 NIMASK = Kmem::Pic_map_base + 0x04,
21 INTENNUM = Kmem::Pic_map_base + 0x08,
22 INTDISNUM = Kmem::Pic_map_base + 0x0c,
23 INTENABLEH = Kmem::Pic_map_base + 0x10,
24 INTENABLEL = Kmem::Pic_map_base + 0x14,
25 INTTYPEH = Kmem::Pic_map_base + 0x18,
26 INTTYPEL = Kmem::Pic_map_base + 0x1c,
27 NIPRIORITY7 = Kmem::Pic_map_base + 0x20,
28 NIPRIORITY0 = Kmem::Pic_map_base + 0x3c,
29 NIVECSR = Kmem::Pic_map_base + 0x40,
30 FIVECSR = Kmem::Pic_map_base + 0x44,
31 INTSRCH = Kmem::Pic_map_base + 0x48,
32 INTSRCL = Kmem::Pic_map_base + 0x4c,
33 INTFRCH = Kmem::Pic_map_base + 0x50,
34 INTFRCL = Kmem::Pic_map_base + 0x54,
35 NIPNDH = Kmem::Pic_map_base + 0x58,
36 NIPNDL = Kmem::Pic_map_base + 0x5c,
37 FIPNDH = Kmem::Pic_map_base + 0x60,
38 FIPNDL = Kmem::Pic_map_base + 0x64,
41 INTCTL_FIAD = 1 << 19, // Fast Interrupt Arbiter Rise ARM Level
42 INTCTL_NIAD = 1 << 20, // Normal Interrupt Arbiter Rise ARM Level
43 INTCTL_FIDIS = 1 << 21, // Fast Interrupt Disable
44 INTCTL_NIDIS = 1 << 22, // Normal Interrupt Disable
48 // ---------------------------------------------------------------------
49 IMPLEMENTATION [arm && imx]:
51 #include "boot_info.h"
53 #include "initcalls.h"
56 #include "irq_chip_generic.h"
62 class Imx_pin : public Irq_pin
65 explicit Imx_pin(unsigned irq) { payload()[0] = irq; }
66 unsigned irq() const { return payload()[0]; }
75 Irq_chip::hw_chip->free(Irq::self(this), irq());
76 replace<Sw_irq_pin>();
83 assert (cpu_lock.test());
84 Io::write<Mword>(irq(), Pic::INTDISNUM); // disable pin
89 Imx_pin::do_mask_and_ack()
91 assert (cpu_lock.test());
93 Io::write<Mword>(irq(), Pic::INTDISNUM); // disable pin
108 assert (cpu_lock.test());
109 Io::write<Mword>(irq(), Pic::INTENNUM);
115 Imx_pin::check_debug_irq()
117 return !Vkey::check_(irq());
122 Imx_pin::set_cpu(unsigned)
126 class Irq_chip_arm_x : public Irq_chip_gen
132 Irq_chip_arm_x::setup(Irq_base *irq, unsigned irqnum)
134 if (irqnum < Config::Max_num_dirqs)
135 irq->pin()->replace<Imx_pin>(irqnum);
138 IMPLEMENT FIASCO_INIT
141 static Irq_chip_arm_x _ia;
142 Irq_chip::hw_chip = &_ia;
144 Io::write<Mword>(0, INTCTL);
145 Io::write<Mword>(0x10, NIMASK); // Do not disable any normal interrupts
147 Io::write<Mword>(0, INTTYPEH); // All interrupts generate normal interrupts
148 Io::write<Mword>(0, INTTYPEL);
150 // Init interrupt priorities
151 for (int i = 0; i < 8; ++i)
152 Io::write<Mword>(0x1111, NIPRIORITY7 + (i * 4)); // low addresses start with 7
156 Pic::Status Pic::disable_all_save()
163 void Pic::restore_all( Status /*s*/ )
167 PUBLIC static inline NEEDS["io.h"]
168 Unsigned32 Pic::pending()
170 return Io::read<Mword>(NIVECSR) >> 16;
174 Mword Pic::is_pending(Mword &irqs, Mword irq)
179 //---------------------------------------------------------------------------
180 IMPLEMENTATION [debug && imx]:
184 Imx_pin::pin_type() const
185 { return "HW i.MX IRQ"; }