/**
* 'IRQ' module.
- *
+ *
* This module handles the 'R' command that
* provides IRQ attachment and listing functions.
*/
Jdb_module::Action_code
Jdb_attach_irq::action( int cmd, void *&args, char const *&, int & )
{
- if (cmd!=0)
+ if (cmd)
return NOTHING;
if ((char*)args == &subcmd)
{
- switch(subcmd)
- {
- case 'l': // list
- {
- Irq *r;
- putchar('\n');
+ switch (subcmd)
+ {
+ case 'l': // list
+ {
+ Irq *r;
+ putchar('\n');
for (unsigned i = 0; i < Config::Max_num_dirqs; ++i)
- {
- r = static_cast<Irq*>(Irq_chip::hw_chip->irq(i));
- if (!r)
- continue;
- printf("IRQ %02x/%02d\n", i, i);
- }
- }
- return NOTHING;
- }
+ {
+ r = static_cast<Irq*>(Irq_chip::hw_chip->irq(i));
+ if (!r)
+ continue;
+ printf("IRQ %02x/%02d\n", i, i);
+ }
+ return NOTHING;
+ }
+ }
}
return NOTHING;
}
#define FIASCO_JDB_CMP_VTABLE(n, o) \
extern char n[]; \
char const *const *z = reinterpret_cast<char const* const*>(o); \
- return *z == n + 12 ? (o) : 0
+ return *z == n + 3 * sizeof(Mword) ? (o) : 0
PUBLIC static
void
Jdb_thread::print_partner(Thread *t, int task_format = 0)
{
- Kobject *o;
+ Sender *p = t->partner();
if (!(t->state(false) & Thread_receiving))
{
return;
}
- if (!t->partner())
+ if (!p)
{
printf("%*s ", task_format, "-");
return;
}
- if (Kobject_dbg::is_kobj(o = Kobject::pointer_to_obj(t->partner())))
+ if (Kobject *o = Kobject::pointer_to_obj(p))
{
char flag = '?';
const char *n = o->kobj_type();
printf("%*.lx%c", task_format, o->dbg_info()->dbg_id(), flag);
}
else
- printf("\033[31;1m%p\033[m ", t->partner());
+ printf("\033[31;1m%p\033[m ", p);
}
private:
static Mword read_board_id();
+ struct id_pair {
+ unsigned mask, id;
+ };
+ static id_pair ids[];
};
// ------------------------------------------------------------------------
-INTERFACE [arm && realview && realview_eb]:
+IMPLEMENTATION [arm && realview]:
-EXTENSION class Board_check
-{
- enum {
- id_mask = 0x1ffffe00, id_val = 0x01400400,
- };
+#include "initcalls.h"
+
+// ------------------------------------------------------------------------
+IMPLEMENTATION [arm && realview && realview_eb]:
+
+Board_check::id_pair Board_check::ids[] FIASCO_INITDATA = {
+ { 0x1ffffe00, 0x01400400 },
};
// ------------------------------------------------------------------------
-INTERFACE [arm && realview && realview_pb11mp]:
+IMPLEMENTATION [arm && realview && realview_pb11mp]:
-EXTENSION class Board_check
-{
- enum {
- id_mask = 0x0fffff00, id_val = 0x0159f500,
- };
+Board_check::id_pair Board_check::ids[] FIASCO_INITDATA = {
+ { 0x0fffff00, 0x0159f500 },
};
// ------------------------------------------------------------------------
-INTERFACE [arm && realview && realview_pbx]:
+IMPLEMENTATION [arm && realview && realview_pbx]:
-EXTENSION class Board_check
-{
- enum {
- id_mask = 0xffffff00, id_val = 0x1182f500,
- };
+Board_check::id_pair Board_check::ids[] FIASCO_INITDATA = {
+ { 0xffffff00, 0x1182f500 }, // board
+ { 0xffffff00, 0x01780500 }, // qemu
};
// ------------------------------------------------------------------------
SYS_ID = Kmem::System_regs_map_base + 0x0,
};
-IMPLEMENT static
+IMPLEMENT static FIASCO_INIT
Mword
Board_check::read_board_id()
{ return Io::read<Mword>(SYS_ID); }
-IMPLEMENT static
+IMPLEMENT static FIASCO_INIT
void
Board_check::check_board()
{
id >> 28, (id >> 16) & 0xfff, (id >> 12) & 0xf,
(id >> 8) & 0xf, id & 0xff);
- if ((id & id_mask) != id_val)
- {
- printf(" Invalid System ID for this kernel config\n"
- " Expected (%08lx & %08x) == %08x\n"
- " Stopping.\n", id, id_mask, id_val);
- while (1)
- Proc::halt();
- }
+ for (unsigned i = 0; i < (sizeof(ids) / sizeof(ids[0])); ++i)
+ if ((id & ids[i].mask) == ids[i].id)
+ return;
+
+ printf(" Invalid System ID for this kernel config\n");
+ for (unsigned i = 0; i < (sizeof(ids) / sizeof(ids[0])); ++i)
+ printf(" Expected (%08lx & %08x) == %08x%s\n",
+ id, ids[i].mask, ids[i].id,
+ i + 1 < (sizeof(ids) / sizeof(ids[0])) ? ", or" : "");
+ printf(" Stopping.\n");
+ while (1)
+ Proc::halt();
}
STATIC_INITIALIZEX_P(Board_check, check_board, GDB_INIT_PRIO);
Cpu(unsigned id) { set_id(id); }
+
+ struct Ids {
+ Mword _pfr[2], _dfr0, _afr0, _mmfr[4];
+ };
+ void id_init();
+
+ enum {
+ Copro_dbg_model_not_supported = 0,
+ Copro_dbg_model_v6 = 2,
+ Copro_dbg_model_v6_1 = 3,
+ Copro_dbg_model_v7 = 4,
+ };
+
+ unsigned copro_dbg_model() const { return _cpu_id._dfr0 & 0xf; }
+
private:
static Cpu *_boot_cpu;
unsigned _phys_id;
+ Ids _cpu_id;
};
// ------------------------------------------------------------------------
enum {
Cp15_c1_ee = 1 << 25,
Cp15_c1_nmfi = 1 << 27,
- Cp15_c1_tre = 1 << 28,
- Cp15_c1_afe = 1 << 29,
Cp15_c1_te = 1 << 30,
+ Cp15_c1_rao_sbop = (0xf << 3) | (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23),
Cp15_c1_cache_bits = Cp15_c1_cache
| Cp15_c1_insn_cache,
Cp15_c1_generic = Cp15_c1_mmu
| (Config::Cp15_c1_use_alignment_check ? Cp15_c1_alignment_check : 0)
| Cp15_c1_branch_predict
+ | Cp15_c1_rao_sbop
| Cp15_c1_high_vector,
};
};
Cp15_c1_ha = 1 << 17,
Cp15_c1_ee = 1 << 25,
Cp15_c1_nmfi = 1 << 27,
- Cp15_c1_tre = 1 << 28,
- Cp15_c1_afe = 1 << 29,
Cp15_c1_te = 1 << 30,
+ Cp15_c1_rao_sbop = (0xf << 3) | (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23),
Cp15_c1_cache_bits = Cp15_c1_cache
| Cp15_c1_insn_cache,
| (Config::Cp15_c1_use_alignment_check ? Cp15_c1_alignment_check : 0)
| Cp15_c1_branch_predict
| Cp15_c1_high_vector
+ | Cp15_c1_rao_sbop
| (Config::Cp15_c1_use_a9_swp_enable ? Cp15_c1_sw : 0),
Smp_enable = 0x41,
early_init_platform();
Mem_unit::flush_cache();
-
- print_infos();
}
_phys_id = Proc::cpu_id();
init_tz();
+
+ id_init();
+
+ print_infos();
+}
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && !armv6plus]:
+
+IMPLEMENT
+void
+Cpu::id_init()
+{
+}
+
+//---------------------------------------------------------------------------
+IMPLEMENTATION [arm && armv6plus]:
+
+IMPLEMENT
+void
+Cpu::id_init()
+{
+ __asm__("mrc p15, 0, %0, c0, c1, 0": "=r" (_cpu_id._pfr[0]));
+ __asm__("mrc p15, 0, %0, c0, c1, 1": "=r" (_cpu_id._pfr[1]));
+ __asm__("mrc p15, 0, %0, c0, c1, 2": "=r" (_cpu_id._dfr0));
+ __asm__("mrc p15, 0, %0, c0, c1, 3": "=r" (_cpu_id._afr0));
+ __asm__("mrc p15, 0, %0, c0, c1, 4": "=r" (_cpu_id._mmfr[0]));
+ __asm__("mrc p15, 0, %0, c0, c1, 5": "=r" (_cpu_id._mmfr[1]));
+ __asm__("mrc p15, 0, %0, c0, c1, 6": "=r" (_cpu_id._mmfr[2]));
+ __asm__("mrc p15, 0, %0, c0, c1, 7": "=r" (_cpu_id._mmfr[3]));
}
//---------------------------------------------------------------------------
Cpu::print_infos()
{}
+// ------------------------------------------------------------------------
+IMPLEMENTATION [debug && armv6plus]:
+
+PRIVATE
+void
+Cpu::id_print_infos()
+{
+ printf("ID_PFR0: %08lx\n", _cpu_id._pfr[0]);
+ printf("ID_PFR1: %08lx\n", _cpu_id._pfr[1]);
+ printf("ID_DFR0: %08lx\n", _cpu_id._dfr0);
+ printf("ID_AFR0: %08lx\n", _cpu_id._afr0);
+ printf("ID_MMFR0: %08lx\n", _cpu_id._mmfr[0]);
+ printf("ID_MMFR1: %08lx\n", _cpu_id._mmfr[1]);
+ printf("ID_MMFR2: %08lx\n", _cpu_id._mmfr[2]);
+ printf("ID_MMFR3: %08lx\n", _cpu_id._mmfr[3]);
+}
+
+// ------------------------------------------------------------------------
+IMPLEMENTATION [debug && !armv6plus]:
+
+PRIVATE
+void
+Cpu::id_print_infos()
+{
+}
+
// ------------------------------------------------------------------------
IMPLEMENTATION [debug]:
-PRIVATE static
+PRIVATE
void
Cpu::print_infos()
{
printf("Cache config: %s\n", Config::cache_enabled ? "ON" : "OFF");
+ id_print_infos();
}
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && perf_cnt && (armca8 || armca9)]:
+#include "cpu.h"
+
char const *Perf_cnt::perf_type_str = "ACor";
int Perf_cnt::_nr_counters;
+PRIVATE static
+bool
+Perf_cnt::is_avail()
+{ return Cpu::boot_cpu()->copro_dbg_model() == Cpu::Copro_dbg_model_v7; }
+
PRIVATE static
void
Perf_cnt::set_event_type(int counter_nr, int event)
{
+ if (!is_avail())
+ return;
+
pmnxsel(counter_nr);
evtsel(event);
}
Mword
Perf_cnt::read_cycle_cnt()
{
+ if (!is_avail())
+ return 0;
return ccnt();
}
unsigned long
Perf_cnt::read_counter(int counter_nr)
{
+ if (!is_avail())
+ return 0;
if (counter_nr >= _nr_counters)
return ccnt();
pmnxsel(counter_nr);
return pmcnt();
}
-
PUBLIC static
unsigned
Perf_cnt::mon_event_type(int nr)
{
+ if (!is_avail())
+ return 0;
+
if (nr >= _nr_counters)
return 0xff;
pmnxsel(nr);
void
Perf_cnt::init_cpu()
{
+ if (!is_avail())
+ return;
+
_nr_counters = (pmnc() >> 11) & 0x1f;
pmnc(PMNC_ENABLE | PMNC_PERF_RESET | PMNC_CNT_RESET);
useren(1);
}
-
-
// ------------------------------------------------------------------------
IMPLEMENTATION [arm && perf_cnt]:
class Ipc_gate_ctl : public Kobject_h<Ipc_gate_ctl, Kobject_iface>
{
+private:
+ enum Operation
+ {
+ Op_bind = 0x10,
+ Op_get_info = 0x11,
+ };
};
class Ipc_gate : public Kobject
switch (in->values[0])
{
- case 0x10:
+ case Op_bind:
return bind_thread(self, rights, f, in, out);
- case 0x11:
+ case Op_get_info:
return get_infos(self, rights, f, in, out);
default:
return static_cast<Ipc_gate_obj*>(this)->kobject_invoke(self, rights, f, in, out);
INTERFACE[mp]:
+#include "per_cpu_data.h"
#include "spin_lock.h"
EXTENSION class Ipi
INTERFACE[mp && debug]:
-#include "per_cpu_data.h"
-
EXTENSION class Ipi
{
public:
: public Kobject_h<Irq_sender, Irq>,
public Ipc_sender<Irq_sender>
{
+public:
+ Mword kobject_size() const { return sizeof(*this); }
+
private:
Irq_sender(Irq_sender &);
#include "obj_space.h"
#include "spin_lock.h"
#include "ref_obj.h"
+#include "slab_cache_anon.h"
class Ram_quota;
class Context;
// startup code that runs after console I/O is initialized
static void stage2();
-
};
IMPLEMENTATION:
#define STATIC_INITIALIZER_P(f, p) \
__STATIC_INITIALIZER_P(f,func_##f,p)
-/// mark f as static initailizer
+/// mark f as static initailizer
#define STATIC_INITIALIZER(f) \
__STATIC_INITIALIZER(f,func_##f)
//@}
/// static initialization of singleton (static) classes
/**
- * The classes that should be initialized must provide
+ * The classes that should be initialized must provide
* a init() member function that takes no arguments.
*/
//@{
-/** mark class c to be statically initialized via its init
+/** mark class c to be statically initialized via its init
* function and with priority p
*/
#define STATIC_INITIALIZE_P(c,p) \
#define STATIC_INITIALIZE(c) \
__STATIC_INITIALIZER(c::init, class_##c)
-/** mark class c to be statically initialized via its init
+/** mark class c to be statically initialized via its init
* function and with priority p
*/
#define STATIC_INITIALIZEX_P(c,func,p) \
#include "static_init.h"
#include "irq.h"
-STATIC_INITIALIZER_P(uart_console_init_stage1 ,UART_INIT_PRIO);
+STATIC_INITIALIZER_P(uart_console_init_stage1, UART_INIT_PRIO);
STATIC_INITIALIZER (uart_console_init_stage2);
static void uart_console_init_stage1()
# CONFIG_IRQ_SPINNER is not set
CONFIG_WATCHDOG=y
CONFIG_SERIAL=y
-CONFIG_JDB=y
-# CONFIG_JDB_LOGGING is not set
-CONFIG_JDB_DISASM=y
-CONFIG_JDB_GZIP=y
-# CONFIG_JDB_ACCOUNTING is not set
-# CONFIG_JDB_MISC is not set
+# CONFIG_JDB is not set
CONFIG_POWERSAVE_GETCHAR=y
# CONFIG_WARN_NONE is not set
CONFIG_WARN_WARNING=y
# CONFIG_MAINTAINER_MODE is not set
CONFIG_LABEL=""
CONFIG_EXPERIMENTAL=y
-CONFIG_PERF_CNT=y
CONFIG_BIT32=y
CONFIG_WARN_LEVEL=1
CONFIG_XARCH="ia32"
$werror = 1 if have_warn_opt("error");
if (!have_warn_opt("static-construction")) {
- push @ignore_funcs, ("__static_initialization_and_destruction_0");
- push @ignore_funcs, ("_GLOBAL__I\\.\\S*");
+ push @ignore_funcs, ("(_Z41)?__static_initialization_and_destruction_0(ii\\.clone\\.\\d+)?");
+ push @ignore_funcs, ("_GLOBAL__(sub_)?I\\.\\S*");
+ push @ignore_funcs, ("_GLOBAL__sub_I__Z\\S*");
push @ignore_funcs, ("global constructors keyed to \\S*");
push @ignore_funcs, ("T\\.\\d+");
}
*/
/**
- * \brief
+ * \brief CPU sets.
* \ingroup l4_scheduler_api
*/
typedef struct l4_sched_cpu_set_t
/**
- * \brief
+ * \brief Scheduler parameter set.
* \ingroup l4_scheduler_api
*/
typedef struct l4_sched_param_t
{
- /**
- * Timeslice in micro seconds.
- */
- l4_cpu_time_t quantum;
-
- /**
- * Priority for scheduling.
- */
- unsigned prio;
-
- /**
- * CPU affinity.
- */
- l4_sched_cpu_set_t affinity;
-
+ l4_cpu_time_t quantum; ///< Timeslice in micro seconds.
+ unsigned prio; ///< Priority for scheduling.
+ l4_sched_cpu_set_t affinity; ///< CPU affinity.
} l4_sched_param_t;
/**
- * \brief
+ * \brief Construct scheduler parameter.
* \ingroup l4_scheduler_api
*/
L4_INLINE l4_sched_param_t
{
case PT_L4_STACK: return "L4_STACK";
case PT_L4_KIP: return "L4_KIP";
+ case PT_L4_AUX: return "L4_AUX";
case PT_GNU_EH_FRAME: return "GNU_EH_FRAME";
case PT_GNU_STACK: return "GNU_STACK";
case PT_GNU_RELRO: return "GNU_RELRO";
{
shared_mem_t *s;
l4re_ds_t shm_ds = L4_INVALID_CAP;
- l4re_namespace_t tmp = L4_INVALID_CAP;
+ l4re_namespace_t shm_cap;
long r = -L4_ENOMEM;
+ shm_cap = l4re_get_env_cap(shm_name);
+ if (l4_is_invalid_cap(shm_cap))
+ return -L4_ENOENT;
+
if (l4_is_invalid_cap(shm_ds = l4re_util_cap_alloc()))
- goto out;
+ return -L4_ENOMEM;
if ((r = l4re_ma_alloc(shm_size, shm_ds, 0)))
- goto out;
+ goto out_shm_free_cap;
if ((r = l4re_rm_attach((void **)&s, shm_size, L4RE_RM_SEARCH_ADDR, shm_ds,
0, L4_PAGESHIFT)))
- goto out;
+ goto out_shm_free_mem;
s->_first_chunk = 0;
- r = -L4_ENOMEM;
- if (l4_is_invalid_cap(tmp = l4re_util_cap_alloc()))
- goto out;
-
- tmp = l4re_get_env_cap(shm_name);
- if (l4_is_invalid_cap(tmp))
- {
- r = -L4_ENOENT;
- goto out;
- }
-
- if ((r = l4re_ns_register_obj_srv(tmp, "shm", shm_ds, L4RE_NS_REGISTER_RW)))
- goto out;
+ r = L4_EOK;
+ if ((r = l4re_ns_register_obj_srv(shm_cap, "shm", shm_ds, L4RE_NS_REGISTER_RW)))
+ r = -L4_EINVAL;
l4re_rm_detach_unmap((l4_addr_t)s, L4RE_THIS_TASK_CAP);
- r = L4_EOK;
+ return r;
-out:
- if (!l4_is_invalid_cap(tmp))
- l4re_util_cap_free(tmp);
+out_shm_free_mem:
+ l4re_ma_free(shm_ds);
+out_shm_free_cap:
+ l4re_util_cap_free(shm_ds);
return r;
}
r, signal->_sigcap, l4_debugger_global_id(signal->_sigcap),
thread);
l4re_util_cap_free(signal->_sigcap);
- goto out;
}
out:
projects / l4.git / commitdiff