mfd: as3722: Documentation for oc_pg_ctrl masking

Update Documentation for device tree update for
optional oc_pg_ctrl_masking feature

Bug 1518725
Bug 1419425

Change-Id: I309533849d48d61aefebd8f477e79b79ed4127fb
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/423185
(cherry picked from commit 824a87782ac13779f9e8e21e847c4b6dac653208)
Reviewed-on: http://git-master/r/424061
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

diff --git a/Documentation/devicetree/bindings/mfd/as3722.txt b/Documentation/devicetree/bindings/mfd/as3722.txt
index 31ebf795f13883e973bb074ae0a814a75c0a0316..a5e88c658dd8425d61193164232959a9a9a1f265 100644 (file)
--- a/Documentation/devicetree/bindings/mfd/as3722.txt
+++ b/Documentation/devicetree/bindings/mfd/as3722.txt
@@ -46,6 +46,19 @@ Optional properties:
 - ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on
        i2c scl/sda pins. Missing this will disable internal pullup on i2c
        scl/sda lines.
+- ams,oc-pg-mask: Enable or disable various powergood or overcurrent or
+       ac_ok mask. The multiple values can be ORed when provided the
+       value of this property. include/dt-binding/mfd/as3722 defines the
+       macro for different masks.
+               AS3722_OC_PG_MASK_AC_OK: AC_OK PG_OC mask
+               AS3722_OC_PG_MASK_GPIO3
+               AS3722_OC_PG_MASK_GPIO4
+               AS3722_OC_PG_MASK_GPIO5
+               AS3722_OC_PG_MASK_PWRGOOD_SD0
+               AS3722_OC_PG_MASK_OVCURR_SD0
+               AS3722_OC_PG_MASK_VRESFALL
+               AS3722_OC_PG_MASK_POWERGOOD_SD6
+               AS3722_OC_PG_MASK_OVCURR_SD6
 
 Optional submodule and their properties:
 =======================================

diff --git a/include/dt-bindings/mfd/as3722.h b/include/dt-bindings/mfd/as3722.h
index 2a4b10a6e3b63284677154bfbbb040bf036060a9..c11f286e4f98bdc3ae34a68a6f9f325697420b7e 100644 (file)
--- a/include/dt-bindings/mfd/as3722.h
+++ b/include/dt-bindings/mfd/as3722.h
@@ -60,4 +60,14 @@
 #define AS3722_IRQ_OCCUR_ALARM_SD6     30
 #define AS3722_IRQ_ADC                 31
 
+/* Power Good OC Mask macro */
+#define AS3722_OC_PG_MASK_AC_OK            0x1
+#define AS3722_OC_PG_MASK_GPIO3            0x2
+#define AS3722_OC_PG_MASK_GPIO4            0x4
+#define AS3722_OC_PG_MASK_GPIO5            0x8
+#define AS3722_OC_PG_MASK_PWRGOOD_SD0      0x10
+#define AS3722_OC_PG_MASK_OVCURR_SD0       0x20
+#define AS3722_OC_PG_MASK_POWERGOOD_SD6    0x40
+#define AS3722_OC_PG_MASK_OVCURR_SD6       0x80
+
 #endif /* __DT_BINDINGS_AS3722_H__ */