as3722->battery_backup_charge_mode = pval;
skip_chg_param:
+ of_property_read_u32(np, "ams,oc-pg-mask", &as3722->oc_pg_mask);
dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
return 0;
}
as3722->battery_backup_enable_bypass =
pdata->battery_backup_enable_bypass;
as3722->battery_backup_charge_mode = pdata->battery_backup_charge_mode;
+ as3722->oc_pg_mask = pdata->oc_pg_mask;
return 0;
}
goto scrub;
}
}
+ if (as3722->oc_pg_mask) {
+ unsigned int mask1 = 0;
+ unsigned int mask2 = 0;
+ unsigned int oc_pg_mask = as3722->oc_pg_mask;
+
+ if (oc_pg_mask & AS3722_OC_PG_MASK_AC_OK)
+ mask1 |= AS3722_PG_AC_OK_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO3)
+ mask1 |= AS3722_PG_GPIO3_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO4)
+ mask1 |= AS3722_PG_GPIO4_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_GPIO5)
+ mask1 |= AS3722_PG_GPIO5_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_PWRGOOD_SD0)
+ mask1 |= AS3722_PG_PWRGOOD_SD0_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_OVCURR_SD0)
+ mask1 |= AS3722_PG_OVCURR_SD0_MASK;
+
+ if (oc_pg_mask & AS3722_OC_PG_MASK_POWERGOOD_SD6)
+ mask2 |= AS3722_PG_POWERGOOD_SD6_MASK;
+ if (oc_pg_mask & AS3722_OC_PG_MASK_OVCURR_SD6)
+ mask2 |= AS3722_PG_OVCURR_SD6_MASK;
+
+ ret = as3722_update_bits(as3722, AS3722_OC_PG_CTRL_REG,
+ mask1, mask1);
+ if (ret < 0) {
+ dev_err(as3722->dev, "oc_pg_ctrl update failed: %d\n",
+ ret);
+ goto scrub;
+ }
+ ret = as3722_update_bits(as3722, AS3722_OC_PG_CTRL2_REG,
+ mask2, mask2);
+ if (ret < 0) {
+ dev_err(as3722->dev, "oc_pg_ctrl2 update failed: %d\n",
+ ret);
+ goto scrub;
+ }
+ }
ret = mfd_add_devices(&i2c->dev, -1, as3722_devs,
ARRAY_SIZE(as3722_devs), NULL, 0,
regmap_irq_get_domain(as3722->irq_data));
AS3722_NUM_GPIO,
};
+/* Power Good OC Mask macro */
+#define AS3722_OC_PG_MASK_AC_OK 0x1
+#define AS3722_OC_PG_MASK_GPIO3 0x2
+#define AS3722_OC_PG_MASK_GPIO4 0x4
+#define AS3722_OC_PG_MASK_GPIO5 0x8
+#define AS3722_OC_PG_MASK_PWRGOOD_SD0 0x10
+#define AS3722_OC_PG_MASK_OVCURR_SD0 0x20
+#define AS3722_OC_PG_MASK_POWERGOOD_SD6 0x40
+#define AS3722_OC_PG_MASK_OVCURR_SD6 0x80
+
/*
* struct as3722_pinctrl_platform_data: Pincontrol platform data.
* @pin: name of pin.
bool battery_backup_enable_bypass;
u32 backup_battery_charge_current;
u32 battery_backup_charge_mode;
+ u32 oc_pg_mask;
};
#endif
#define AS3722_BBCMODE_ACT_STBY 2
#define AS3722_BBCMODE_ACT_STBY_OFF 3
+#define AS3722_PG_AC_OK_INV_MASK BIT(0)
+#define AS3722_PG_AC_OK_MASK BIT(1)
+#define AS3722_PG_GPIO3_MASK BIT(2)
+#define AS3722_PG_GPIO4_MASK BIT(3)
+#define AS3722_PG_GPIO5_MASK BIT(4)
+#define AS3722_PG_PWRGOOD_SD0_MASK BIT(5)
+#define AS3722_PG_OVCURR_SD0_MASK BIT(6)
+#define AS3722_PG_VRESFALL_MASK BIT(7)
+
+#define AS3722_OC_PG_INVERT_MASK BIT(0)
+#define AS3722_PG_VMASK_TIME_MASK (3 << 1)
+#define AS3722_PG_SD6_OVC_ALARM_MASK (7 << 3)
+#define AS3722_PG_POWERGOOD_SD6_MASK BIT(6)
+#define AS3722_PG_OVCURR_SD6_MASK BIT(7)
+
/* Interrupt IDs */
enum as3722_irq {
AS3722_IRQ_LID,
bool battery_backup_enable_bypass;
u32 backup_battery_charge_current;
u32 battery_backup_charge_mode;
+ u32 oc_pg_mask;
};