ufs: tegra: update UFS device/hc clock frequencies.

-update UFS device CAR clock to 19.2 MHz
-update ufshc max clk to 204 MHz.
-When ufshc cock is set to 204 MHz, corresponding
HCLKDIV value should also be updated to 204 to generate
correct 1 micro sec tick.

Bug 200163672
Bug 200160928

Change-Id: Ibf0fc98302cf65b3a42c33354ecdd396443ee317
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/1148719
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>

diff --git a/drivers/scsi/ufs/ufs-tegra.h b/drivers/scsi/ufs/ufs-tegra.h
index 891876f1d05f7269fb201a7e74ada48c5ec139b6..a9cf8d285a0395f6a857a99b8a560f615120c8f8 100644 (file)
--- a/drivers/scsi/ufs/ufs-tegra.h
+++ b/drivers/scsi/ufs/ufs-tegra.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * Authors:
  *      VenkataJagadish.p      <vjagadish@nvidia.com>
@@ -82,8 +82,8 @@
 #define UFS_AUX_ADDR_RANGE     0x18
 
 /*UFS Clock Defines*/
-#define UFSHC_CLK_FREQ         51000000
-#define UFSDEV_CLK_FREQ                38400000
+#define UFSHC_CLK_FREQ         204000000
+#define UFSDEV_CLK_FREQ                19200000
 
 enum ufs_state {
        UFSHC_INIT,
@@ -97,7 +97,7 @@ enum ufs_state {
  * HCLKFrequency in MHz.
  * HCLKDIV is used to generate 1usec tick signal used by Unipro.
  */
-#define UFS_VNDR_HCLKDIV_1US_TICK      0x33
+#define UFS_VNDR_HCLKDIV_1US_TICK      0xCC
 
 
 /*UFS host controller vendor specific registers */