ufs: tegra: update UFS device/hc clock frequencies.
-update UFS device CAR clock to 19.2 MHz
-update ufshc max clk to 204 MHz.
-When ufshc cock is set to 204 MHz, corresponding
HCLKDIV value should also be updated to 204 to generate
correct 1 micro sec tick.
Bug
200163672
Bug
200160928
Change-Id: Ibf0fc98302cf65b3a42c33354ecdd396443ee317
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/
1148719
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>