]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree - system/ip/axi_pwm_coprocessor_1.0/example_designs/
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / ip / axi_pwm_coprocessor_1.0 / example_designs /
drwxr-xr-x   ..
drwxr-xr-x - bfm_design
drwxr-xr-x - debug_hw_design