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Martin Jerabek [Thu, 12 May 2016 11:50:16 +0000 (13:50 +0200)]
system: updated scripts
Martin Jerabek [Thu, 12 May 2016 11:49:54 +0000 (13:49 +0200)]
sja1000: synchronous with AXI, duplex register access (WIP)
Martin Jerabek [Thu, 12 May 2016 11:46:31 +0000 (13:46 +0200)]
removed generated file
Martin Jerabek [Wed, 11 May 2016 12:08:14 +0000 (14:08 +0200)]
sja1000 core, linux drivers
Martin Jerabek [Wed, 11 May 2016 12:06:43 +0000 (14:06 +0200)]
bitstream file renamed
Martin Jerabek [Sun, 8 May 2016 23:38:49 +0000 (01:38 +0200)]
added sja1000 IP
Martin Jerabek [Tue, 3 May 2016 22:20:30 +0000 (00:20 +0200)]
petalinux: mc & talloc fix
Martin Jerabek [Tue, 3 May 2016 21:11:04 +0000 (23:11 +0200)]
petalinux: added Midnight Commander
Martin Jerabek [Tue, 3 May 2016 20:58:27 +0000 (22:58 +0200)]
petalinux: fixed booting stuff
Martin Jerabek [Fri, 1 Apr 2016 08:44:59 +0000 (10:44 +0200)]
system: build fix, removed generated HDL wrappers
Martin Jerabek [Wed, 30 Mar 2016 17:53:20 +0000 (19:53 +0200)]
Makefile: build bootscript
Martin Jerabek [Wed, 30 Mar 2016 17:52:41 +0000 (19:52 +0200)]
Makefile fixes
Martin Jerabek [Tue, 29 Mar 2016 19:22:07 +0000 (21:22 +0200)]
updated bootscript, added "How to build" to README.txt
Martin Jerabek [Tue, 29 Mar 2016 18:36:18 +0000 (20:36 +0200)]
petalinux: added canutils, dropbear (SSH server), libs
Martin Jerabek [Tue, 29 Mar 2016 18:35:06 +0000 (20:35 +0200)]
petalinux: Boot from network (TFTP), NFS root; support for custom u-boot bootscript
Martin Jerabek [Fri, 25 Mar 2016 20:22:07 +0000 (21:22 +0100)]
Added latester (sources in submodule) and dependencies (libpopt, libtalloc)
Martin Jerabek [Fri, 25 Mar 2016 13:38:00 +0000 (14:38 +0100)]
Added patched xilinx_can module, canhwtstamp testing app
Martin Jerabek [Fri, 25 Mar 2016 13:37:12 +0000 (14:37 +0100)]
added system and petalinux configuration, scripts, makefiles
TODO: remove HDL wrappers?
Pavel Pisa [Fri, 4 Mar 2016 10:03:37 +0000 (11:03 +0100)]
Initial commit - CAN benchmark FPGA design and software for MicroZed board.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
projects / fpga / zynq / canbench-sw.git / log