dcsimpledrv: refresh IP after trailing spaces removal.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/system/ip/dcsimpledrv_1.0/component.xml b/system/ip/dcsimpledrv_1.0/component.xml
index 142a6da8ba37da35fb966420cf5c9d91de24cae0..2c85f2d9a0d3dac3120c42a57175907c8aac65ce 100644 (file)
--- a/system/ip/dcsimpledrv_1.0/component.xml
+++ b/system/ip/dcsimpledrv_1.0/component.xml
@@ -266,7 +266,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>cee40dbc</spirit:value>
+            <spirit:value>acba5639</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -282,7 +282,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>cee40dbc</spirit:value>
+            <spirit:value>acba5639</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -954,8 +954,8 @@
         <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>dcsimpledrv_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>5</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2017-07-26T16:47:18Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>6</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2017-07-26T18:35:48Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="pikron.com:user:dcsimpledrv:1.0_ARCHIVE_LOCATION">/home/pi/fpga/zynq/canbech-sw/system/ip/dcsimpledrv_1.0</xilinx:tag>
       </xilinx:tags>
@@ -964,7 +964,7 @@
       <xilinx:xilinxVersion>2016.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="ab027bc6"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="493665f4"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="170f08c4"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="472e04e3"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="d7c0b28e"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ce3109b2"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c7ddb8f2"/>