trasfer_rq : out std_logic;
trasfer_rq_dbl : out std_logic;
- ready_for_rq : in std_logic
+ ready_for_rq : in std_logic;
+
+ lcd_reset_bit : out std_logic
);
end component display_16bit_cmd_data_bus_v1_0_S00_AXI;
signal trasfer_rq_dbl : std_logic;
signal ready_for_rq : std_logic;
+ signal lcd_reset_bit: std_logic;
+ signal lcd_fsm_res_n: std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
trasfer_rq => trasfer_rq,
trasfer_rq_dbl => trasfer_rq_dbl,
- ready_for_rq => ready_for_rq
+ ready_for_rq => ready_for_rq,
+
+ lcd_reset_bit => lcd_reset_bit
);
-- Instantiation of Axi Bus Interface M00_AXI
clk_in => fsm_clk,
clk_en => '1',
- lcd_res_n => lcd_res_n,
+ lcd_res_n => lcd_fsm_res_n,
lcd_cs_n => lcd_cs_n,
lcd_wr_n => lcd_wr_n,
lcd_rd_n => lcd_rd_n,
fsm_clk <= s00_axi_aclk;
fsm_rst <= not s00_axi_aresetn;
+ lcd_res_n <= lcd_fsm_res_n and not lcd_reset_bit;
+
m00_axi_init_axi_txn <= '0';
irq_rq_out <= '0';
trasfer_rq : out std_logic;
trasfer_rq_dbl : out std_logic;
- ready_for_rq : in std_logic
+ ready_for_rq : in std_logic;
+
+ lcd_reset_bit : out std_logic
);
end display_16bit_cmd_data_bus_v1_0_S00_AXI;
-- Add user logic here
-
+ lcd_reset_bit <= slv_reg0(1);
-- User logic ends
end arch_imp;