]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commitdiff
microzed_apo: 16 bit bus LCD: Add register bit for program initiated reset.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 14 Feb 2017 16:29:53 +0000 (17:29 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 14 Feb 2017 16:29:53 +0000 (17:29 +0100)
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/ip/display_16bit_cmd_data_bus_1.0/hdl/display_16bit_cmd_data_bus_v1_0.vhd
system/ip/display_16bit_cmd_data_bus_1.0/hdl/display_16bit_cmd_data_bus_v1_0_S00_AXI.vhd

index 0bfe913f3a28fa2885bda88a7466fffcaf0bd462..5b79e25efd342f22e590e260ba0b2b6b9518e117 100644 (file)
@@ -119,7 +119,9 @@ architecture arch_imp of display_16bit_cmd_data_bus_v1_0 is
 
                trasfer_rq      : out std_logic;
                trasfer_rq_dbl  : out std_logic;
-               ready_for_rq    : in std_logic
+               ready_for_rq    : in std_logic;
+
+               lcd_reset_bit   : out std_logic
                );
        end component display_16bit_cmd_data_bus_v1_0_S00_AXI;
 
@@ -201,6 +203,8 @@ architecture arch_imp of display_16bit_cmd_data_bus_v1_0 is
        signal  trasfer_rq_dbl : std_logic;
        signal  ready_for_rq : std_logic;
 
+       signal  lcd_reset_bit: std_logic;
+       signal  lcd_fsm_res_n: std_logic;
 begin
 
 -- Instantiation of Axi Bus Interface S00_AXI
@@ -237,7 +241,9 @@ display_16bit_cmd_data_bus_v1_0_S00_AXI_inst : display_16bit_cmd_data_bus_v1_0_S
 
                trasfer_rq => trasfer_rq,
                trasfer_rq_dbl => trasfer_rq_dbl,
-               ready_for_rq => ready_for_rq
+               ready_for_rq => ready_for_rq,
+
+               lcd_reset_bit => lcd_reset_bit
        );
 
 -- Instantiation of Axi Bus Interface M00_AXI
@@ -287,7 +293,7 @@ display_16bit_cmd_data_bus_v1_0_io_fsm_inst: display_16bit_cmd_data_bus_v1_0_io_
                clk_in => fsm_clk,
                clk_en => '1',
 
-               lcd_res_n => lcd_res_n,
+               lcd_res_n => lcd_fsm_res_n,
                lcd_cs_n => lcd_cs_n,
                lcd_wr_n => lcd_wr_n,
                lcd_rd_n => lcd_rd_n,
@@ -306,6 +312,8 @@ display_16bit_cmd_data_bus_v1_0_io_fsm_inst: display_16bit_cmd_data_bus_v1_0_io_
        fsm_clk <= s00_axi_aclk;
        fsm_rst <= not s00_axi_aresetn;
 
+       lcd_res_n <= lcd_fsm_res_n and not lcd_reset_bit;
+
        m00_axi_init_axi_txn <= '0';
 
        irq_rq_out <= '0';
index 182a83c0e4ad55c63520dd6ff0730483b0c31582..3acfd541680bf13637542678e9aa760696e865a3 100644 (file)
@@ -86,7 +86,9 @@ entity display_16bit_cmd_data_bus_v1_0_S00_AXI is
 
                trasfer_rq      : out std_logic;
                trasfer_rq_dbl  : out std_logic;
-               ready_for_rq    : in std_logic
+               ready_for_rq    : in std_logic;
+
+               lcd_reset_bit   : out std_logic
        );
 end display_16bit_cmd_data_bus_v1_0_S00_AXI;
 
@@ -563,7 +565,7 @@ begin
 
 
        -- Add user logic here
-
+       lcd_reset_bit <= slv_reg0(1);
        -- User logic ends
 
 end arch_imp;