microzed_apo: Divide DE2 compatible FPGA_IO terminals to the A, B and C continuous...

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/system/src/constrs/microzed_apo-rev1.xdc b/system/src/constrs/microzed_apo-rev1.xdc
index ab1129b84c88e06bed7c33da68f70ef606390c77..722aca9312e84b5ba8097d7d017ce48677875915 100644 (file)
--- a/system/src/constrs/microzed_apo-rev1.xdc
+++ b/system/src/constrs/microzed_apo-rev1.xdc
@@ -64,44 +64,44 @@ set_property DIRECTION OUT [get_ports [list {SPEAKER}]];
 #    FPGA IO connector and PMOD1 and 2
 # ------------------------------------------------------------------------------
 
-set_property PACKAGE_PIN N18 [get_ports {FPGA_IO[1]}]; # JX1_LVDS_12_P (34)
-set_property PACKAGE_PIN P19 [get_ports {FPGA_IO[2]}]; # JX1_LVDS_12_N (34)
-set_property PACKAGE_PIN T11 [get_ports {FPGA_IO[3]}]; # JX1_LVDS_0_P (34)
-set_property PACKAGE_PIN T10 [get_ports {FPGA_IO[4]}]; # JX1_LVDS_0_N (34)
-set_property PACKAGE_PIN U13 [get_ports {FPGA_IO[5]}]; # JX1_LVDS_2_P (34)
-set_property PACKAGE_PIN V13 [get_ports {FPGA_IO[6]}]; # JX1_LVDS_2_N (34)
-set_property PACKAGE_PIN T14 [get_ports {FPGA_IO[7]}]; # JX1_LVDS_4_P (34)
-set_property PACKAGE_PIN T15 [get_ports {FPGA_IO[8]}]; # JX1_LVDS_4_N (34)
-set_property PACKAGE_PIN Y16 [get_ports {FPGA_IO[9]}]; # JX1_LVDS_6_P (34)
-set_property PACKAGE_PIN Y17 [get_ports {FPGA_IO[10]}]; # JX1_LVDS_6_N (34)
-
-set_property PACKAGE_PIN T16 [get_ports {FPGA_IO[13]}]; # JX1_LVDS_8_P (34)
-set_property PACKAGE_PIN U17 [get_ports {FPGA_IO[14]}]; # JX1_LVDS_8_N (34)
-set_property PACKAGE_PIN U14 [get_ports {FPGA_IO[15]}]; # JX1_LVDS_10_P (34)
-set_property PACKAGE_PIN U15 [get_ports {FPGA_IO[16]}]; # JX1_LVDS_10_N (34)
-set_property PACKAGE_PIN T20 [get_ports {FPGA_IO[17]}]; # JX1_LVDS_14_P (34)
-set_property PACKAGE_PIN U20 [get_ports {FPGA_IO[18]}]; # JX1_LVDS_14_N (34)
-set_property PACKAGE_PIN Y18 [get_ports {FPGA_IO[19]}]; # JX1_LVDS_16_P (34)
-set_property PACKAGE_PIN Y19 [get_ports {FPGA_IO[20]}]; # JX1_LVDS_16_N (34)
-set_property PACKAGE_PIN R16 [get_ports {FPGA_IO[21]}]; # JX1_LVDS_18_P (34)
-set_property PACKAGE_PIN R17 [get_ports {FPGA_IO[22]}]; # JX1_LVDS_18_N (34)
-set_property PACKAGE_PIN V17 [get_ports {FPGA_IO[23]}]; # PMOD1[6] JX1_LVDS_20_P (34)
-set_property PACKAGE_PIN V18 [get_ports {FPGA_IO[24]}]; # PMOD1[7] JX1_LVDS_20_N (34)
-set_property PACKAGE_PIN N17 [get_ports {FPGA_IO[25]}]; # PMOD1[4] JX1_LVDS_22_P (34)
-set_property PACKAGE_PIN P18 [get_ports {FPGA_IO[26]}]; # PMOD1[5] JX1_LVDS_22_N (34)
-set_property PACKAGE_PIN P15 [get_ports {FPGA_IO[27]}]; # PMOD2[2] JX1_LVDS_23_P (34)
-set_property PACKAGE_PIN P16 [get_ports {FPGA_IO[28]}]; # PMOD2[3] JX1_LVDS_23_N (34)
-
-set_property PACKAGE_PIN W18 [get_ports {FPGA_IO[31]}]; # PMOD2[0] JX1_LVDS_21_P (34)
-set_property PACKAGE_PIN W19 [get_ports {FPGA_IO[32]}]; # PMOD2[2] JX1_LVDS_21_N (34)
-set_property PACKAGE_PIN T17 [get_ports {FPGA_IO[33]}]; # PMOD2[4] JX1_LVDS_19_P (34)
-set_property PACKAGE_PIN R18 [get_ports {FPGA_IO[34]}]; # PMOD2[5] JX1_LVDS_19_N (34)
-set_property PACKAGE_PIN V16 [get_ports {FPGA_IO[35]}]; # PMOD2[6] JX1_LVDS_17_P (34)
-set_property PACKAGE_PIN W16 [get_ports {FPGA_IO[36]}]; # PMOD2[7] JX1_LVDS_17_N (34)
-set_property PACKAGE_PIN V20 [get_ports {FPGA_IO[37]}]; # PMOD1[2] JX1_LVDS_15_P (34)
-set_property PACKAGE_PIN W20 [get_ports {FPGA_IO[38]}]; # PMOD1[3] JX1_LVDS_15_N (34)
-set_property PACKAGE_PIN N20 [get_ports {FPGA_IO[39]}]; # PMOD1[0] JX1_LVDS_13_P (34)
-set_property PACKAGE_PIN P20 [get_ports {FPGA_IO[40]}]; # PMOD1[1] JX1_LVDS_13_N (34)
+set_property PACKAGE_PIN N18 [get_ports {FPGA_IO_A[1]}]; # JX1_LVDS_12_P (34)
+set_property PACKAGE_PIN P19 [get_ports {FPGA_IO_A[2]}]; # JX1_LVDS_12_N (34)
+set_property PACKAGE_PIN T11 [get_ports {FPGA_IO_A[3]}]; # JX1_LVDS_0_P (34)
+set_property PACKAGE_PIN T10 [get_ports {FPGA_IO_A[4]}]; # JX1_LVDS_0_N (34)
+set_property PACKAGE_PIN U13 [get_ports {FPGA_IO_A[5]}]; # JX1_LVDS_2_P (34)
+set_property PACKAGE_PIN V13 [get_ports {FPGA_IO_A[6]}]; # JX1_LVDS_2_N (34)
+set_property PACKAGE_PIN T14 [get_ports {FPGA_IO_A[7]}]; # JX1_LVDS_4_P (34)
+set_property PACKAGE_PIN T15 [get_ports {FPGA_IO_A[8]}]; # JX1_LVDS_4_N (34)
+set_property PACKAGE_PIN Y16 [get_ports {FPGA_IO_A[9]}]; # JX1_LVDS_6_P (34)
+set_property PACKAGE_PIN Y17 [get_ports {FPGA_IO_A[10]}]; # JX1_LVDS_6_N (34)
+
+set_property PACKAGE_PIN T16 [get_ports {FPGA_IO_B[13]}]; # JX1_LVDS_8_P (34)
+set_property PACKAGE_PIN U17 [get_ports {FPGA_IO_B[14]}]; # JX1_LVDS_8_N (34)
+set_property PACKAGE_PIN U14 [get_ports {FPGA_IO_B[15]}]; # JX1_LVDS_10_P (34)
+set_property PACKAGE_PIN U15 [get_ports {FPGA_IO_B[16]}]; # JX1_LVDS_10_N (34)
+set_property PACKAGE_PIN T20 [get_ports {FPGA_IO_B[17]}]; # JX1_LVDS_14_P (34)
+set_property PACKAGE_PIN U20 [get_ports {FPGA_IO_B[18]}]; # JX1_LVDS_14_N (34)
+set_property PACKAGE_PIN Y18 [get_ports {FPGA_IO_B[19]}]; # JX1_LVDS_16_P (34)
+set_property PACKAGE_PIN Y19 [get_ports {FPGA_IO_B[20]}]; # JX1_LVDS_16_N (34)
+set_property PACKAGE_PIN R16 [get_ports {FPGA_IO_B[21]}]; # JX1_LVDS_18_P (34)
+set_property PACKAGE_PIN R17 [get_ports {FPGA_IO_B[22]}]; # JX1_LVDS_18_N (34)
+set_property PACKAGE_PIN V17 [get_ports {FPGA_IO_B[23]}]; # PMOD1[6] JX1_LVDS_20_P (34)
+set_property PACKAGE_PIN V18 [get_ports {FPGA_IO_B[24]}]; # PMOD1[7] JX1_LVDS_20_N (34)
+set_property PACKAGE_PIN N17 [get_ports {FPGA_IO_B[25]}]; # PMOD1[4] JX1_LVDS_22_P (34)
+set_property PACKAGE_PIN P18 [get_ports {FPGA_IO_B[26]}]; # PMOD1[5] JX1_LVDS_22_N (34)
+set_property PACKAGE_PIN P15 [get_ports {FPGA_IO_B[27]}]; # PMOD2[2] JX1_LVDS_23_P (34)
+set_property PACKAGE_PIN P16 [get_ports {FPGA_IO_B[28]}]; # PMOD2[3] JX1_LVDS_23_N (34)
+
+set_property PACKAGE_PIN W18 [get_ports {FPGA_IO_C[31]}]; # PMOD2[0] JX1_LVDS_21_P (34)
+set_property PACKAGE_PIN W19 [get_ports {FPGA_IO_C[32]}]; # PMOD2[2] JX1_LVDS_21_N (34)
+set_property PACKAGE_PIN T17 [get_ports {FPGA_IO_C[33]}]; # PMOD2[4] JX1_LVDS_19_P (34)
+set_property PACKAGE_PIN R18 [get_ports {FPGA_IO_C[34]}]; # PMOD2[5] JX1_LVDS_19_N (34)
+set_property PACKAGE_PIN V16 [get_ports {FPGA_IO_C[35]}]; # PMOD2[6] JX1_LVDS_17_P (34)
+set_property PACKAGE_PIN W16 [get_ports {FPGA_IO_C[36]}]; # PMOD2[7] JX1_LVDS_17_N (34)
+set_property PACKAGE_PIN V20 [get_ports {FPGA_IO_C[37]}]; # PMOD1[2] JX1_LVDS_15_P (34)
+set_property PACKAGE_PIN W20 [get_ports {FPGA_IO_C[38]}]; # PMOD1[3] JX1_LVDS_15_N (34)
+set_property PACKAGE_PIN N20 [get_ports {FPGA_IO_C[39]}]; # PMOD1[0] JX1_LVDS_13_P (34)
+set_property PACKAGE_PIN P20 [get_ports {FPGA_IO_C[40]}]; # PMOD1[1] JX1_LVDS_13_N (34)
 
 # ------------------------------------------------------------------------------
 #    Camera 1 pins