]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commitdiff
AXI PWM Coprocessor: try harder to remove remnants of INIT_AXI_TXN signal.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Fri, 20 May 2016 15:39:09 +0000 (17:39 +0200)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Mon, 16 Jan 2017 16:57:20 +0000 (17:57 +0100)
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/ip/axi_pwm_coprocessor_1.0/component.xml
system/ip/axi_pwm_coprocessor_1.0/example_designs/bfm_design/axi_pwm_coprocessor_v1_0_tb.v
system/ip/axi_pwm_coprocessor_1.0/example_designs/bfm_design/design.tcl

index b6b055446ca19211de891132e2edf5d9a9651f81..2c267af502950d937715176f82174eb938e42fe9 100644 (file)
           </spirit:wireTypeDefs>
         </spirit:wire>
       </spirit:port>
-      <spirit:port>
-        <spirit:name>m00_axi_init_axi_txn</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
       <spirit:port>
         <spirit:name>m00_axi_error</spirit:name>
         <spirit:wire>
index e107bd8302c2d56e9054dfb5737ac075590935c0..448ff6276644afcc6f14f81776424a783e2b8733 100644 (file)
@@ -20,7 +20,6 @@ module axi_pwm_coprocessor_v1_0_tb;
        reg tb_ACLK;
        reg tb_ARESETn;
 
-       reg M00_AXI_INIT_AXI_TXN;
        wire M00_AXI_TXN_DONE;
        wire M00_AXI_ERROR;
 
index d4a46b22407cbd092489bef29e9df56ab9a1af2b..5112fef2380c839fb1ca14dc2d2db1951574ffdf 100644 (file)
@@ -24,7 +24,6 @@ proc create_ipi_design { offsetfile design_name } {
        connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_pwm_coprocessor_0/S00_AXI_ARESETN]
 
        # Create External ports
-       set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
        set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
        set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
 
@@ -36,7 +35,6 @@ connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI_LITE] [get_bd_intf_pins axi_
        # Create port connections
        connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/S_AXI_LITE_ACLK] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ACLK]
        connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/S_AXI_LITE_ARESETN] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ARESETN]
-       connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_INIT_AXI_TXN]
        connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_ERROR]
        connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins axi_pwm_coprocessor_0/M00_AXI_TXN_DONE]