system/ip/axi_pwm_coprocessor_1.0/example_designs/bfm_design/axi_pwm_coprocessor_v1_0_tb.v

   1
   2 `timescale 1 ns / 1 ps
   3
   4 `include "axi_pwm_coprocessor_v1_0_tb_include.vh"
   5
   6 // lite_response Type Defines
   7 `define RESPONSE_OKAY 2'b00
   8 `define RESPONSE_EXOKAY 2'b01
   9 `define RESP_BUS_WIDTH 2
  10 `define BURST_TYPE_INCR  2'b01
  11 `define BURST_TYPE_WRAP  2'b10
  12
  13 // AMBA AXI4 Lite Range Constants
  14 `define S00_AXI_MAX_BURST_LENGTH 1
  15 `define S00_AXI_DATA_BUS_WIDTH 32
  16 `define S00_AXI_ADDRESS_BUS_WIDTH 32
  17 `define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
  18
  19 module axi_pwm_coprocessor_v1_0_tb;
  20         reg tb_ACLK;
  21         reg tb_ARESETn;
  22
  23         wire M00_AXI_TXN_DONE;
  24         wire M00_AXI_ERROR;
  25
  26         // Create an instance of the example tb
  27         `BD_WRAPPER dut (.ACLK(tb_ACLK),
  28                                 .ARESETN(tb_ARESETn),
  29                                 .M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
  30                                 .M00_AXI_ERROR(M00_AXI_ERROR),
  31                                 .M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN));
  32
  33         // Local Variables
  34
  35         // AMBA S00_AXI AXI4 Lite Local Reg
  36         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
  37         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
  38         reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
  39         reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
  40         reg [3-1:0]   S00_AXI_mtestProtection_lite;
  41         integer S00_AXI_mtestvectorlite; // Master side testvector
  42         integer S00_AXI_mtestdatasizelite;
  43         integer result_slave_lite;
  44
  45
  46         // Simple Reset Generator and test
  47         initial begin
  48                 tb_ARESETn = 1'b0;
  49           #500;
  50                 // Release the reset on the posedge of the clk.
  51                 @(posedge tb_ACLK);
  52           tb_ARESETn = 1'b1;
  53                 @(posedge tb_ACLK);
  54         end
  55
  56         // Simple Clock Generator
  57         initial tb_ACLK = 1'b0;
  58         always #10 tb_ACLK = !tb_ACLK;
  59
  60         //------------------------------------------------------------------------
  61         // TEST LEVEL API: CHECK_RESPONSE_OKAY
  62         //------------------------------------------------------------------------
  63         // Description:
  64         // CHECK_RESPONSE_OKAY(lite_response)
  65         // This task checks if the return lite_response is equal to OKAY
  66         //------------------------------------------------------------------------
  67         task automatic CHECK_RESPONSE_OKAY;
  68                 input [`RESP_BUS_WIDTH-1:0] response;
  69                 begin
  70                   if (response !== `RESPONSE_OKAY) begin
  71                           $display("TESTBENCH ERROR! lite_response is not OKAY",
  72                                          "\n expected = 0x%h",`RESPONSE_OKAY,
  73                                          "\n actual   = 0x%h",response);
  74                     $stop;
  75                   end
  76                 end
  77         endtask
  78
  79         //------------------------------------------------------------------------
  80         // TEST LEVEL API: COMPARE_LITE_DATA
  81         //------------------------------------------------------------------------
  82         // Description:
  83         // COMPARE_LITE_DATA(expected,actual)
  84         // This task checks if the actual data is equal to the expected data.
  85         // X is used as don't care but it is not permitted for the full vector
  86         // to be don't care.
  87         //------------------------------------------------------------------------
  88         `define S_AXI_DATA_BUS_WIDTH 32
  89         task automatic COMPARE_LITE_DATA;
  90                 input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
  91                 input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
  92                 begin
  93                         if (expected === 'hx || actual === 'hx) begin
  94                                 $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
  95                     result_slave_lite = 0;
  96                     $stop;
  97                   end
  98
  99                         if (actual != expected) begin
 100                                 $display("TESTBENCH ERROR! Data expected is not equal to actual.",
 101                                          "\nexpected = 0x%h",expected,
 102                                          "\nactual   = 0x%h",actual);
 103                     result_slave_lite = 0;
 104                     $stop;
 105                   end
 106                         else
 107                         begin
 108                            $display("TESTBENCH Passed! Data expected is equal to actual.",
 109                                     "\n expected = 0x%h",expected,
 110                                     "\n actual   = 0x%h",actual);
 111                         end
 112                 end
 113         endtask
 114
 115         task automatic S00_AXI_TEST;
 116                 begin
 117                         $display("---------------------------------------------------------");
 118                         $display("EXAMPLE TEST : S00_AXI");
 119                         $display("Simple register write and read example");
 120                         $display("---------------------------------------------------------");
 121
 122                         S00_AXI_mtestvectorlite = 0;
 123                         S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
 124                         S00_AXI_mtestProtection_lite = 0;
 125                         S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
 126
 127                          result_slave_lite = 1;
 128
 129                         for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
 130                         begin
 131                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
 132                                                      S00_AXI_mtestProtection_lite,
 133                                                      S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
 134                                                      S00_AXI_mtestdatasizelite,
 135                                                      S00_AXI_lite_response);
 136                           $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
 137                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 138                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
 139                                                      S00_AXI_mtestProtection_lite,
 140                                                      S00_AXI_rd_data_lite,
 141                                                      S00_AXI_lite_response);
 142                           $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
 143                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 144                           COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
 145                           $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
 146                           S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
 147                         end
 148
 149                         $display("---------------------------------------------------------");
 150                         $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
 151                                 if ( result_slave_lite ) begin
 152                                         $display("PTGEN_TEST: PASSED!");
 153                                 end     else begin
 154                                         $display("PTGEN_TEST: FAILED!");
 155                                 end
 156                         $display("---------------------------------------------------------");
 157                 end
 158         endtask
 159
 160         // Create the test vectors
 161         initial begin
 162                 // When performing debug enable all levels of INFO messages.
 163                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 164                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 165                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 166                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 167                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 168
 169                 dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
 170
 171                 // Create test data vectors
 172                 S00_AXI_test_data_lite[0] = 32'h0101FFFF;
 173                 S00_AXI_test_data_lite[1] = 32'habcd0001;
 174                 S00_AXI_test_data_lite[2] = 32'hdead0011;
 175                 S00_AXI_test_data_lite[3] = 32'hbeef0011;
 176         end
 177
 178         // Drive the BFM
 179         initial begin
 180                 // Wait for end of reset
 181                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 182                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 183                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 184                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 185                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 186
 187                 S00_AXI_TEST();
 188
 189         end
 190
 191         // Drive the BFM
 192         initial begin
 193                 // Wait for end of reset
 194                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 195                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 196                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 197                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 198                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 199
 200                 M00_AXI_INIT_AXI_TXN = 1'b0;
 201                 #500 M00_AXI_INIT_AXI_TXN = 1'b1;
 202
 203                 $display("EXAMPLE TEST M00_AXI:");
 204                 wait( M00_AXI_TXN_DONE == 1'b1);
 205                 $display("M00_AXI: PTGEN_TEST_FINISHED!");
 206                 if ( M00_AXI_ERROR ) begin
 207                   $display("PTGEN_TEST: FAILED!");
 208                 end else begin
 209                   $display("PTGEN_TEST: PASSED!");
 210                 end
 211
 212         end
 213
 214 endmodule