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<xilinx:displayName>display_16bit_cmd_data_bus_v1.0</xilinx:displayName>
- <xilinx:coreRevision>2</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2017-02-09T09:19:30Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>4</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2017-02-14T13:49:08Z</xilinx:coreCreationDateTime>
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<xilinx:tag xilinx:name="user.org:user:display_16bit_cmd_data_bus:1.0_ARCHIVE_LOCATION">/home/pi/fpga/zynq/canbech-sw/system/ip/display_16bit_cmd_data_bus_1.0</xilinx:tag>
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
- S_AXI_RREADY : in std_logic
+ S_AXI_RREADY : in std_logic;
+
+ data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ dc_out : out std_logic;
+
+ trasfer_rq : out std_logic;
+ trasfer_rq_dbl : out std_logic;
+ ready_for_rq : in std_logic
);
end component display_16bit_cmd_data_bus_v1_0_S00_AXI;
);
end component display_16bit_cmd_data_bus_v1_0_M00_AXI;
+ component display_16bit_cmd_data_bus_v1_0_io_fsm is
+ generic (
+ data_width : integer := 32;
+ lcd_io_width : integer := 16;
+ lcd_bus_clkdiv : integer := 1
+ );
+ port (
+ reset_in : in std_logic;
+
+ clk_in : in std_logic;
+ clk_en : in std_logic;
+
+ lcd_res_n : out std_logic;
+ lcd_cs_n : out std_logic;
+ lcd_wr_n : out std_logic;
+ lcd_rd_n : out std_logic;
+ lcd_dc : out std_logic;
+ lcd_data : inout std_logic_vector(lcd_io_width-1 downto 0);
+
+ data_out : in std_logic_vector(data_width-1 downto 0);
+ dc_out : in std_logic;
+
+ trasfer_rq : in std_logic;
+ trasfer_rq_dbl : in std_logic;
+ ready_for_rq : out std_logic
+ );
+ end component;
+
signal m00_axi_init_axi_txn : std_logic;
signal m00_axi_error : std_logic;
signal m00_axi_txn_done : std_logic;
+ signal fsm_clk : std_logic;
+ signal fsm_rst : std_logic;
+
+ signal data_out : std_logic_vector(31 downto 0);
+ signal dc_out : std_logic;
+
+ signal trasfer_rq : std_logic;
+ signal trasfer_rq_dbl : std_logic;
+ signal ready_for_rq : std_logic;
+
begin
-- Instantiation of Axi Bus Interface S00_AXI
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
- S_AXI_RREADY => s00_axi_rready
+ S_AXI_RREADY => s00_axi_rready,
+
+ data_out => data_out,
+ dc_out => dc_out,
+
+ trasfer_rq => trasfer_rq,
+ trasfer_rq_dbl => trasfer_rq_dbl,
+ ready_for_rq => ready_for_rq
);
-- Instantiation of Axi Bus Interface M00_AXI
M_AXI_RREADY => m00_axi_rready
);
+display_16bit_cmd_data_bus_v1_0_io_fsm_inst: display_16bit_cmd_data_bus_v1_0_io_fsm
+ generic map (
+ data_width => 32,
+ lcd_io_width => 16,
+ lcd_bus_clkdiv => 1
+ )
+ port map (
+ reset_in => fsm_rst,
+ clk_in => fsm_clk,
+ clk_en => '1',
+
+ lcd_res_n => lcd_res_n,
+ lcd_cs_n => lcd_cs_n,
+ lcd_wr_n => lcd_wr_n,
+ lcd_rd_n => lcd_rd_n,
+ lcd_dc => lcd_dc,
+ lcd_data => lcd_data,
+
+ data_out => data_out,
+ dc_out => dc_out,
+
+ trasfer_rq => trasfer_rq,
+ trasfer_rq_dbl => trasfer_rq_dbl,
+ ready_for_rq => ready_for_rq
+ );
+
-- Add user logic here
- m00_axi_init_axi_txn <= '0';
+ fsm_clk <= s00_axi_aclk;
+ fsm_rst <= not s00_axi_aresetn;
+
+ m00_axi_init_axi_txn <= '0';
- irq_rq_out <= '0';
+ irq_rq_out <= '0';
- lcd_res_n <= '1';
- lcd_cs_n <= '1';
- lcd_wr_n <= '1';
- lcd_rd_n <= '1';
- lcd_dc <= '0';
-- User logic ends
end arch_imp;
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
- S_AXI_RREADY : in std_logic
+ S_AXI_RREADY : in std_logic;
+
+ data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ dc_out : out std_logic;
+
+ trasfer_rq : out std_logic;
+ trasfer_rq_dbl : out std_logic;
+ ready_for_rq : in std_logic
);
end display_16bit_cmd_data_bus_v1_0_S00_AXI;
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
- if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
+ if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1'
+ and ready_for_rq = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
+
+ data_out <= (others => '0');
+ dc_out <= '0';
+
+ trasfer_rq <= '0';
+ trasfer_rq_dbl <= '0';
else
+ trasfer_rq <= '0';
+
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
+
+ data_out <= S_AXI_WDATA;
+ dc_out <= '0';
+
+ trasfer_rq <= '1';
+ trasfer_rq_dbl <= S_AXI_WSTRB(2);
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
+
+ data_out <= S_AXI_WDATA;
+ dc_out <= '1';
+
+ trasfer_rq <= '1';
+ trasfer_rq_dbl <= S_AXI_WSTRB(2);
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display_16bit_cmd_data_bus_v1_0_io_fsm is
+ generic (
+ data_width : integer := 32;
+ lcd_io_width : integer := 16;
+ lcd_bus_clkdiv : integer := 1
+ );
+ port (
+ reset_in : in std_logic;
+
+ clk_in : in std_logic;
+ clk_en : in std_logic;
+
+ lcd_res_n : out std_logic;
+ lcd_cs_n : out std_logic;
+ lcd_wr_n : out std_logic;
+ lcd_rd_n : out std_logic;
+ lcd_dc : out std_logic;
+ lcd_data : inout std_logic_vector(lcd_io_width-1 downto 0);
+
+ data_out : in std_logic_vector(data_width-1 downto 0);
+ dc_out : in std_logic;
+
+ trasfer_rq : in std_logic;
+ trasfer_rq_dbl : in std_logic;
+ ready_for_rq : out std_logic
+ );
+end display_16bit_cmd_data_bus_v1_0_io_fsm;
+
+architecture arch_imp of display_16bit_cmd_data_bus_v1_0_io_fsm is
+
+ type io_states is (is_iddle, is_wrini, is_wr0, is_wr1,
+ is_wr2, is_wrfin);
+ signal io_state_r : io_states;
+ signal trasfer_rq_dbl_r : std_logic;
+
+ signal div_cnt : natural range 0 to lcd_bus_clkdiv-1;
+ signal data_out_r : std_logic_vector(data_width-1 downto 0);
+ signal dc_out_r : std_logic;
+
+begin
+
+ process is
+ begin
+ wait until rising_edge (clk_in);
+ if ( reset_in = '1' ) then
+ div_cnt <= lcd_bus_clkdiv-1;
+ ready_for_rq <= '0';
+ io_state_r <= is_iddle;
+ lcd_res_n <= '0';
+ lcd_cs_n <= '1';
+ lcd_wr_n <= '1';
+ lcd_rd_n <= '1';
+ lcd_dc <= '1';
+ lcd_data <= (others => 'Z');
+ elsif (clk_en = '1') then
+ lcd_res_n <= '1';
+ if trasfer_rq = '1' and io_state_r = is_iddle then
+ data_out_r <= data_out;
+ dc_out_r <= dc_out;
+ trasfer_rq_dbl_r <= trasfer_rq_dbl;
+ io_state_r <= is_wrini;
+ end if;
+ if (div_cnt /= 0) then
+ div_cnt <= div_cnt - 1;
+ else
+ div_cnt <= lcd_bus_clkdiv-1;
+ case io_state_r is
+
+ when is_iddle =>
+ if trasfer_rq = '1' then
+ ready_for_rq <= '0';
+ io_state_r <= is_wr0;
+ lcd_data <= data_out(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out;
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ lcd_rd_n <= '1';
+ else
+ ready_for_rq <= '1';
+ lcd_data <= (others => 'Z');
+ lcd_cs_n <= '1';
+ lcd_wr_n <= '1';
+ lcd_rd_n <= '1';
+ end if;
+ when is_wrini =>
+ ready_for_rq <= '0';
+ io_state_r <= is_wr0;
+ lcd_data <= data_out_r(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out_r;
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ lcd_rd_n <= '1';
+ when is_wr0 =>
+ ready_for_rq <= '0';
+ io_state_r <= is_wr1;
+ lcd_data <= data_out_r(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out_r;
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '0';
+ when is_wr1 =>
+ ready_for_rq <= '0';
+ io_state_r <= is_wr2;
+ lcd_data <= data_out_r(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out_r;
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '0';
+ when is_wr2 =>
+ ready_for_rq <= '0';
+ io_state_r <= is_wrfin;
+ lcd_data <= data_out_r(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out_r;
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ when is_wrfin =>
+ lcd_data <= data_out_r(lcd_io_width-1 downto 0);
+ lcd_dc <= dc_out_r;
+ if trasfer_rq_dbl_r = '1' then
+ ready_for_rq <= '0';
+ io_state_r <= is_wrini;
+ data_out_r(lcd_io_width-1 downto 0) <=
+ data_out_r(2 * lcd_io_width-1 downto lcd_io_width);
+ trasfer_rq_dbl_r <= '0';
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ else
+ ready_for_rq <= '1';
+ io_state_r <= is_iddle;
+ lcd_data <= (others => 'Z');
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ lcd_cs_n <= '0';
+ lcd_wr_n <= '1';
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end arch_imp;
--- /dev/null
+GHDL=ghdl
+
+core_DIR=../hdl
+core_SRC=display_16bit_cmd_data_bus_v1_0_io_fsm.vhd
+
+tb_DIR=.
+tb_SRC=display_16bit_cmd_data_bus_v1_0_tb.vhd
+
+MODULES=core tb
+
+TOP_COMPONENT = display_16bit_cmd_data_bus_tb
+
+SRC=$(foreach m, $(MODULES), $($(m)_SRC:%=$($(m)_DIR)/%))
+
+$(warning SRC=$(SRC))
+
+#SRC+=mapo_tb.vhd
+
+CFLAGS += -Wall
+
+GHDLFLAGS+=
+ANALYZEFLAGS+=--std=93c --ieee=synopsys -fexplicit -ggdb
+
+#SIM_FLAGS=--stop-time=1000ns #--ieee-asserts=disable
+
+all: test-mapo
+
+convert_bin2bits : convert_bin2bits.o
+
+imem.bits : imem.bin convert_bin2bits
+ ./convert_bin2bits $< >$@
+
+# imem.bits
+test-mapo: analyze-all
+ $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) $(TOP_COMPONENT)
+ $(GHDL) $(GHDLFLAGS) -r $(TOP_COMPONENT) --stop-time=2000ns --vcd=$@.vcd --wave=$@.ghw
+
+analyze-all: $(SRC)
+ $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC)
+
+clean:
+ rm -f convert_bin2bits
+ rm -f *.o
+ $(GHDL) --clean
+ $(RM) work-obj93.cf
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display_16bit_cmd_data_bus_tb is
+end display_16bit_cmd_data_bus_tb;
+
+architecture arch_imp of display_16bit_cmd_data_bus_tb is
+
+ component display_16bit_cmd_data_bus_v1_0_io_fsm is
+ generic (
+ data_width : integer := 32;
+ lcd_io_width : integer := 16;
+ lcd_bus_clkdiv : integer := 1
+ );
+ port (
+ reset_in : in std_logic;
+
+ clk_in : in std_logic;
+ clk_en : in std_logic;
+
+ lcd_res_n : out std_logic;
+ lcd_cs_n : out std_logic;
+ lcd_wr_n : out std_logic;
+ lcd_rd_n : out std_logic;
+ lcd_dc : out std_logic;
+ lcd_data : inout std_logic_vector(lcd_io_width-1 downto 0);
+
+ data_out : in std_logic_vector(data_width-1 downto 0);
+ dc_out : in std_logic;
+
+ trasfer_rq : in std_logic;
+ trasfer_rq_dbl : in std_logic;
+ ready_for_rq : out std_logic
+ );
+ end component;
+
+ constant clk_period : time := 10 ns;
+
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '1';
+
+ signal lcd_res_n : std_logic;
+ signal lcd_cs_n : std_logic;
+ signal lcd_wr_n : std_logic;
+ signal lcd_rd_n : std_logic;
+ signal lcd_dc : std_logic;
+ signal lcd_data : std_logic_vector(15 downto 0);
+
+ signal data_out : std_logic_vector(31 downto 0);
+ signal dc_out : std_logic;
+
+ signal trasfer_rq : std_logic;
+ signal trasfer_rq_dbl : std_logic;
+ signal ready_for_rq : std_logic;
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: display_16bit_cmd_data_bus_v1_0_io_fsm
+ generic map (
+ data_width => 32,
+ lcd_io_width => 16,
+ lcd_bus_clkdiv => 1
+ )
+ port map (
+ reset_in => rst,
+ clk_in => clk,
+ clk_en => '1',
+
+ lcd_res_n => lcd_res_n,
+ lcd_cs_n => lcd_cs_n,
+ lcd_wr_n => lcd_wr_n,
+ lcd_rd_n => lcd_rd_n,
+ lcd_dc => lcd_dc,
+ lcd_data => lcd_data,
+
+ data_out => data_out,
+ dc_out => dc_out,
+
+ trasfer_rq => trasfer_rq,
+ trasfer_rq_dbl => trasfer_rq_dbl,
+ ready_for_rq => ready_for_rq
+ );
+
+ data_out <= "10110001111111111011000100000000";
+
+ clk_process :process
+ begin
+ clk <= '1';
+ wait for clk_period/2;
+ clk <= '0';
+ wait for clk_period/2;
+ end process;
+
+ test_process :process
+ begin
+ trasfer_rq <= '0';
+ trasfer_rq_dbl <= '0';
+ dc_out <= '1';
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ rst <= '0';
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ trasfer_rq <= '1';
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ trasfer_rq <= '0';
+ dc_out <= '0';
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ trasfer_rq <= '1';
+ trasfer_rq_dbl <= '1';
+ wait until rising_edge (clk);
+ trasfer_rq <= '0';
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ wait until rising_edge (clk);
+ end process;
+
+end arch_imp;
projects / fpga / zynq / canbench-sw.git / commitdiff