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(parent: b12ffa9) | patch
microzed_apo: 16 bit bus LCD: Implemented basic write logic.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 14 Feb 2017 13:57:28 +0000 (14:57 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 14 Feb 2017 13:57:28 +0000 (14:57 +0100)
commit7e9e6db9711461505390c6e2fbdb58f4f2a69998
treefe5c297551f73d79b86198781c275e5af89e59a3tree | snapshot
parentb12ffa923d34c6ac9cbc88155d0ea0b7f8d67d83commit | diff
microzed_apo: 16 bit bus LCD: Implemented basic write logic.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/ip/display_16bit_cmd_data_bus_1.0/component.xml diff | blob | history
system/ip/display_16bit_cmd_data_bus_1.0/hdl/display_16bit_cmd_data_bus_v1_0.vhd diff | blob | history
system/ip/display_16bit_cmd_data_bus_1.0/hdl/display_16bit_cmd_data_bus_v1_0_S00_AXI.vhd diff | blob | history
system/ip/display_16bit_cmd_data_bus_1.0/hdl/display_16bit_cmd_data_bus_v1_0_io_fsm.vhd [new file with mode: 0644] blob
system/ip/display_16bit_cmd_data_bus_1.0/tb/Makefile [new file with mode: 0644] blob
system/ip/display_16bit_cmd_data_bus_1.0/tb/display_16bit_cmd_data_bus_v1_0_tb.vhd [new file with mode: 0644] blob
CAN benchmark FPGA design and software for MicroZed board