]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
microzed_apo: Update top level block design to inlcude autio and display and remove...
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Thu, 9 Feb 2017 10:16:46 +0000 (11:16 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Thu, 9 Feb 2017 10:16:46 +0000 (11:16 +0100)
commitb12ffa923d34c6ac9cbc88155d0ea0b7f8d67d83
tree6e0d1105b0c3904f7624b681881ae756ca4751a0
parent6dd9b8ccf692ea6db19e112284536b4970124eb7
microzed_apo: Update top level block design to inlcude autio and display and remove sja1000.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
system/src/top/top.bd