]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blobdiff - system/ip/sja1000_1.0/component.xml
sja1000: synchronous with AXI, duplex register access (WIP)
[fpga/zynq/canbench-sw.git] / system / ip / sja1000_1.0 / component.xml
index f2c06f4dff879101eca5805f39cfb43e9998559a..d9ea2a291923a19bf141029f742cf466235b6ea0 100644 (file)
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4030548c</spirit:value>
+            <spirit:value>586400b8</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4030548c</spirit:value>
+            <spirit:value>586400b8</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
-      <spirit:file>
-        <spirit:name>hdl/can_register_syn.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
-      </spirit:file>
       <spirit:file>
         <spirit:name>hdl/can_defines.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_top_raw.v</spirit:name>
+        <spirit:name>hdl/can_ifc_axi_sync_duplex.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_ibo.v</spirit:name>
+        <spirit:name>hdl/can_top_raw.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_acf.v</spirit:name>
+        <spirit:name>hdl/can_ibo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_ifc_axi.v</spirit:name>
+        <spirit:name>hdl/can_acf.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
         <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
-      <spirit:file>
-        <spirit:name>hdl/can_register_syn.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
-      </spirit:file>
       <spirit:file>
         <spirit:name>hdl/can_defines.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_top_raw.v</spirit:name>
+        <spirit:name>hdl/can_ifc_axi_sync_duplex.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_ibo.v</spirit:name>
+        <spirit:name>hdl/can_top_raw.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_acf.v</spirit:name>
+        <spirit:name>hdl/can_ibo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>hdl/can_ifc_axi.v</spirit:name>
+        <spirit:name>hdl/can_acf.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
         <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
         <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
       </xilinx:taxonomies>
       <xilinx:displayName>sja1000_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>3</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2016-05-11T10:03:38Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>8</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2016-05-11T17:43:43Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:sja1000:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0</xilinx:tag>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2015.4</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5dbb9758"/>
+      <xilinx:xilinxVersion>2016.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="fa0dead8"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ca22a6c3"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0b6c5764"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="25cd449f"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="2af143f4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8a3bfb41"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="edbec00a"/>