X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/blobdiff_plain/8a74eec78d9c75dac52446d98a484b774e85e2b9..3a3155d08b2b359f32117faa35ba38f13d78c263:/system/ip/sja1000_1.0/component.xml
diff --git a/system/ip/sja1000_1.0/component.xml b/system/ip/sja1000_1.0/component.xml
index f2c06f4..d9ea2a2 100644
--- a/system/ip/sja1000_1.0/component.xml
+++ b/system/ip/sja1000_1.0/component.xml
@@ -307,7 +307,7 @@
viewChecksum
- 4030548c
+ 586400b8
@@ -322,7 +322,7 @@
viewChecksum
- 4030548c
+ 586400b8
@@ -795,11 +795,6 @@
verilogSource
xil_defaultlib
-
- hdl/can_register_syn.v
- verilogSource
- xil_defaultlib
-
hdl/can_defines.v
verilogSource
@@ -836,22 +831,22 @@
xil_defaultlib
- hdl/can_top_raw.v
+ hdl/can_ifc_axi_sync_duplex.v
verilogSource
xil_defaultlib
- hdl/can_ibo.v
+ hdl/can_top_raw.v
verilogSource
xil_defaultlib
- hdl/can_acf.v
+ hdl/can_ibo.v
verilogSource
xil_defaultlib
- hdl/can_ifc_axi.v
+ hdl/can_acf.v
verilogSource
xil_defaultlib
@@ -882,12 +877,6 @@
USED_IN_ipstatic
xil_defaultlib
-
- hdl/can_register_syn.v
- verilogSource
- USED_IN_ipstatic
- xil_defaultlib
-
hdl/can_defines.v
verilogSource
@@ -931,25 +920,24 @@
xil_defaultlib
- hdl/can_top_raw.v
+ hdl/can_ifc_axi_sync_duplex.v
verilogSource
- USED_IN_ipstatic
xil_defaultlib
- hdl/can_ibo.v
+ hdl/can_top_raw.v
verilogSource
USED_IN_ipstatic
xil_defaultlib
- hdl/can_acf.v
+ hdl/can_ibo.v
verilogSource
USED_IN_ipstatic
xil_defaultlib
- hdl/can_ifc_axi.v
+ hdl/can_acf.v
verilogSource
USED_IN_ipstatic
xil_defaultlib
@@ -1014,17 +1002,17 @@
AXI_Peripheral
sja1000_v1.0
- 3
- 2016-05-11T10:03:38Z
+ 8
+ 2016-05-11T17:43:43Z
/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0
- 2015.4
-
+ 2016.1
+
-
+