system/ip/servo_led_ps2_1.0/hdl/servo_led_ps2_v1_0.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity servo_led_ps2_v1_0 is
   6         generic (
   7                 -- Users to add parameters here
   8
   9                 -- User parameters ends
  10                 -- Do not modify the parameters beyond this line
  11
  12
  13                 -- Parameters of Axi Slave Bus Interface S00_AXI
  14                 C_S00_AXI_DATA_WIDTH    : integer       := 32;
  15                 C_S00_AXI_ADDR_WIDTH    : integer       := 5
  16         );
  17         port (
  18                 -- Users to add ports here
  19                 SERVO1          : out std_logic;
  20                 SERVO2          : out std_logic;
  21                 SERVO3          : out std_logic;
  22                 SERVO4          : inout std_logic;
  23                 -- User ports ends
  24                 -- Do not modify the ports beyond this line
  25
  26
  27                 -- Ports of Axi Slave Bus Interface S00_AXI
  28                 s00_axi_aclk    : in std_logic;
  29                 s00_axi_aresetn : in std_logic;
  30                 s00_axi_awaddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
  31                 s00_axi_awprot  : in std_logic_vector(2 downto 0);
  32                 s00_axi_awvalid : in std_logic;
  33                 s00_axi_awready : out std_logic;
  34                 s00_axi_wdata   : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
  35                 s00_axi_wstrb   : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
  36                 s00_axi_wvalid  : in std_logic;
  37                 s00_axi_wready  : out std_logic;
  38                 s00_axi_bresp   : out std_logic_vector(1 downto 0);
  39                 s00_axi_bvalid  : out std_logic;
  40                 s00_axi_bready  : in std_logic;
  41                 s00_axi_araddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
  42                 s00_axi_arprot  : in std_logic_vector(2 downto 0);
  43                 s00_axi_arvalid : in std_logic;
  44                 s00_axi_arready : out std_logic;
  45                 s00_axi_rdata   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
  46                 s00_axi_rresp   : out std_logic_vector(1 downto 0);
  47                 s00_axi_rvalid  : out std_logic;
  48                 s00_axi_rready  : in std_logic
  49         );
  50 end servo_led_ps2_v1_0;
  51
  52 architecture arch_imp of servo_led_ps2_v1_0 is
  53
  54         -- component declaration
  55         component servo_led_ps2_v1_0_S00_AXI is
  56                 generic (
  57                 servo_pwm_width         : integer       := 24;
  58                 C_S_AXI_DATA_WIDTH      : integer       := 32;
  59                 C_S_AXI_ADDR_WIDTH      : integer       := 5
  60                 );
  61                 port (
  62                 S_REG0          : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  63                 servo_pwm_period: out std_logic_vector(servo_pwm_width-1 downto 0);
  64                 servo1_pwm_duty: out std_logic_vector(servo_pwm_width-1 downto 0);
  65                 servo2_pwm_duty: out std_logic_vector(servo_pwm_width-1 downto 0);
  66                 servo3_pwm_duty: out std_logic_vector(servo_pwm_width-1 downto 0);
  67                 servo4_pwm_duty: out std_logic_vector(servo_pwm_width-1 downto 0);
  68
  69                 S_AXI_ACLK      : in std_logic;
  70                 S_AXI_ARESETN   : in std_logic;
  71                 S_AXI_AWADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  72                 S_AXI_AWPROT    : in std_logic_vector(2 downto 0);
  73                 S_AXI_AWVALID   : in std_logic;
  74                 S_AXI_AWREADY   : out std_logic;
  75                 S_AXI_WDATA     : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  76                 S_AXI_WSTRB     : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
  77                 S_AXI_WVALID    : in std_logic;
  78                 S_AXI_WREADY    : out std_logic;
  79                 S_AXI_BRESP     : out std_logic_vector(1 downto 0);
  80                 S_AXI_BVALID    : out std_logic;
  81                 S_AXI_BREADY    : in std_logic;
  82                 S_AXI_ARADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  83                 S_AXI_ARPROT    : in std_logic_vector(2 downto 0);
  84                 S_AXI_ARVALID   : in std_logic;
  85                 S_AXI_ARREADY   : out std_logic;
  86                 S_AXI_RDATA     : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  87                 S_AXI_RRESP     : out std_logic_vector(1 downto 0);
  88                 S_AXI_RVALID    : out std_logic;
  89                 S_AXI_RREADY    : in std_logic
  90                 );
  91         end component servo_led_ps2_v1_0_S00_AXI;
  92
  93         component cnt_div is
  94                 generic (
  95                 cnt_width_g : natural := 4
  96                 );
  97                 port
  98                 (
  99                 clk_i     : in std_logic;                               --clk to divide
 100                 en_i      : in std_logic;                               --enable bit?
 101                 reset_i   : in std_logic;                               --asynch. reset
 102                 ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
 103                 q_out_o   : out std_logic                               --generates puls when counter underflows
 104                 );
 105         end component;
 106
 107         component pulse_gen is
 108                 generic (
 109                 duration_width_g : natural := 4
 110                 );
 111                 port (
 112                 clk_i      : in std_logic;                              --clk to divide
 113                 en_i       : in std_logic;                              --enable bit?
 114                 reset_i    : in std_logic;                              --asynch. reset
 115                 trigger_i  : in std_logic;                              --start to generate pulse
 116                 duration_i : in std_logic_vector(duration_width_g-1 downto 0);--duration/interval of the pulse
 117                 q_out_o    : out std_logic                              --generates pulse for given duration
 118                 );
 119         end component;
 120
 121         constant servo_pwm_width : integer := 24;
 122
 123         signal servo_pwm_period: std_logic_vector(servo_pwm_width-1 downto 0);
 124         signal servo1_pwm_duty: std_logic_vector(servo_pwm_width-1 downto 0);
 125         signal servo2_pwm_duty: std_logic_vector(servo_pwm_width-1 downto 0);
 126         signal servo3_pwm_duty: std_logic_vector(servo_pwm_width-1 downto 0);
 127         signal servo4_pwm_duty: std_logic_vector(servo_pwm_width-1 downto 0);
 128
 129         signal fsm_clk : std_logic;
 130         signal fsm_rst : std_logic;
 131
 132         signal pwm_cycle_start : std_logic;
 133
 134         signal s_reg0   : std_logic_vector(32-1 downto 0);
 135
 136         signal servo1_pwm: std_logic;
 137         signal servo2_pwm: std_logic;
 138         signal servo3_pwm: std_logic;
 139         signal servo4_pwm: std_logic;
 140 begin
 141
 142 -- Instantiation of Axi Bus Interface S00_AXI
 143 servo_led_ps2_v1_0_S00_AXI_inst : servo_led_ps2_v1_0_S00_AXI
 144         generic map (
 145                 servo_pwm_width         => servo_pwm_width,
 146                 C_S_AXI_DATA_WIDTH      => C_S00_AXI_DATA_WIDTH,
 147                 C_S_AXI_ADDR_WIDTH      => C_S00_AXI_ADDR_WIDTH
 148         )
 149         port map (
 150                 S_REG0          => s_reg0,
 151                 servo_pwm_period => servo_pwm_period,
 152                 servo1_pwm_duty => servo1_pwm_duty,
 153                 servo2_pwm_duty => servo2_pwm_duty,
 154                 servo3_pwm_duty => servo3_pwm_duty,
 155                 servo4_pwm_duty => servo4_pwm_duty,
 156
 157                 S_AXI_ACLK      => s00_axi_aclk,
 158                 S_AXI_ARESETN   => s00_axi_aresetn,
 159                 S_AXI_AWADDR    => s00_axi_awaddr,
 160                 S_AXI_AWPROT    => s00_axi_awprot,
 161                 S_AXI_AWVALID   => s00_axi_awvalid,
 162                 S_AXI_AWREADY   => s00_axi_awready,
 163                 S_AXI_WDATA     => s00_axi_wdata,
 164                 S_AXI_WSTRB     => s00_axi_wstrb,
 165                 S_AXI_WVALID    => s00_axi_wvalid,
 166                 S_AXI_WREADY    => s00_axi_wready,
 167                 S_AXI_BRESP     => s00_axi_bresp,
 168                 S_AXI_BVALID    => s00_axi_bvalid,
 169                 S_AXI_BREADY    => s00_axi_bready,
 170                 S_AXI_ARADDR    => s00_axi_araddr,
 171                 S_AXI_ARPROT    => s00_axi_arprot,
 172                 S_AXI_ARVALID   => s00_axi_arvalid,
 173                 S_AXI_ARREADY   => s00_axi_arready,
 174                 S_AXI_RDATA     => s00_axi_rdata,
 175                 S_AXI_RRESP     => s00_axi_rresp,
 176                 S_AXI_RVALID    => s00_axi_rvalid,
 177                 S_AXI_RREADY    => s00_axi_rready
 178         );
 179
 180         -- Add user logic here
 181 cnt_div_inst: cnt_div
 182         generic map (
 183                 cnt_width_g => servo_pwm_width
 184         )
 185         port map (
 186                 clk_i => fsm_clk,
 187                 en_i => '1',
 188                 reset_i => fsm_rst,
 189                 ratio_i =>servo_pwm_period,
 190                 q_out_o => pwm_cycle_start
 191         );
 192
 193 servo1_pwm_inst: pulse_gen
 194         generic map (
 195                 duration_width_g => servo_pwm_width
 196         )
 197         port map (
 198                 clk_i => fsm_clk,
 199                 en_i => '1',
 200                 reset_i => fsm_rst,
 201                 trigger_i => pwm_cycle_start,
 202                 duration_i => servo1_pwm_duty,
 203                 q_out_o => servo1_pwm
 204         );
 205
 206 servo2_pwm_inst: pulse_gen
 207         generic map (
 208                 duration_width_g => servo_pwm_width
 209         )
 210         port map (
 211                 clk_i => fsm_clk,
 212                 en_i => '1',
 213                 reset_i => fsm_rst,
 214                 trigger_i => pwm_cycle_start,
 215                 duration_i => servo2_pwm_duty,
 216                 q_out_o => servo2_pwm
 217         );
 218
 219 servo3_pwm_inst: pulse_gen
 220         generic map (
 221                 duration_width_g => servo_pwm_width
 222         )
 223         port map (
 224                 clk_i => fsm_clk,
 225                 en_i => '1',
 226                 reset_i => fsm_rst,
 227                 trigger_i => pwm_cycle_start,
 228                 duration_i => servo3_pwm_duty,
 229                 q_out_o => servo3_pwm
 230         );
 231
 232 servo4_pwm_inst: pulse_gen
 233         generic map (
 234                 duration_width_g => servo_pwm_width
 235         )
 236         port map (
 237                 clk_i => fsm_clk,
 238                 en_i => '1',
 239                 reset_i => fsm_rst,
 240                 trigger_i => pwm_cycle_start,
 241                 duration_i => servo4_pwm_duty,
 242                 q_out_o => servo4_pwm
 243         );
 244
 245         SERVO1 <= s_reg0(0) xor servo1_pwm;
 246         SERVO2 <= s_reg0(1) xor servo2_pwm;
 247         SERVO3 <= s_reg0(2) xor servo3_pwm;
 248         SERVO4 <= s_reg0(3) xor servo4_pwm when s_reg0(8) = '1'
 249                   else 'Z';
 250
 251         fsm_clk <= s00_axi_aclk;
 252         fsm_rst <= not s00_axi_aresetn;
 253         -- User logic ends
 254
 255 end arch_imp;