2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 entity audio_single_pwm_v1_0_M00_AXI is
7 -- Users to add parameters here
9 -- User parameters ends
10 -- Do not modify the parameters beyond this line
12 -- The master will start generating data from the C_M_START_DATA_VALUE value
13 C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
14 -- The master requires a target slave base address.
15 -- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
16 C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
17 -- Width of M_AXI address bus.
18 -- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
19 C_M_AXI_ADDR_WIDTH : integer := 32;
20 -- Width of M_AXI data bus.
21 -- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
22 C_M_AXI_DATA_WIDTH : integer := 32;
23 -- Transaction number is the number of write
24 -- and read transactions the master will perform as a part of this example memory test.
25 C_M_TRANSACTIONS_NUM : integer := 4
28 -- Users to add ports here
31 -- Do not modify the ports beyond this line
33 -- Initiate AXI transactions
34 INIT_AXI_TXN : in std_logic;
35 -- Asserts when ERROR is detected
36 ERROR : out std_logic;
37 -- Asserts when AXI transactions is complete
38 TXN_DONE : out std_logic;
40 M_AXI_ACLK : in std_logic;
41 -- AXI active low reset signal
42 M_AXI_ARESETN : in std_logic;
43 -- Master Interface Write Address Channel ports. Write address (issued by master)
44 M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
45 -- Write channel Protection type.
46 -- This signal indicates the privilege and security level of the transaction,
47 -- and whether the transaction is a data access or an instruction access.
48 M_AXI_AWPROT : out std_logic_vector(2 downto 0);
49 -- Write address valid.
50 -- This signal indicates that the master signaling valid write address and control information.
51 M_AXI_AWVALID : out std_logic;
52 -- Write address ready.
53 -- This signal indicates that the slave is ready to accept an address and associated control signals.
54 M_AXI_AWREADY : in std_logic;
55 -- Master Interface Write Data Channel ports. Write data (issued by master)
56 M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
58 -- This signal indicates which byte lanes hold valid data.
59 -- There is one write strobe bit for each eight bits of the write data bus.
60 M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
61 -- Write valid. This signal indicates that valid write data and strobes are available.
62 M_AXI_WVALID : out std_logic;
63 -- Write ready. This signal indicates that the slave can accept the write data.
64 M_AXI_WREADY : in std_logic;
65 -- Master Interface Write Response Channel ports.
66 -- This signal indicates the status of the write transaction.
67 M_AXI_BRESP : in std_logic_vector(1 downto 0);
68 -- Write response valid.
69 -- This signal indicates that the channel is signaling a valid write response
70 M_AXI_BVALID : in std_logic;
71 -- Response ready. This signal indicates that the master can accept a write response.
72 M_AXI_BREADY : out std_logic;
73 -- Master Interface Read Address Channel ports. Read address (issued by master)
74 M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
76 -- This signal indicates the privilege and security level of the transaction,
77 -- and whether the transaction is a data access or an instruction access.
78 M_AXI_ARPROT : out std_logic_vector(2 downto 0);
79 -- Read address valid.
80 -- This signal indicates that the channel is signaling valid read address and control information.
81 M_AXI_ARVALID : out std_logic;
82 -- Read address ready.
83 -- This signal indicates that the slave is ready to accept an address and associated control signals.
84 M_AXI_ARREADY : in std_logic;
85 -- Master Interface Read Data Channel ports. Read data (issued by slave)
86 M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
87 -- Read response. This signal indicates the status of the read transfer.
88 M_AXI_RRESP : in std_logic_vector(1 downto 0);
89 -- Read valid. This signal indicates that the channel is signaling the required read data.
90 M_AXI_RVALID : in std_logic;
91 -- Read ready. This signal indicates that the master can accept the read data and response information.
92 M_AXI_RREADY : out std_logic
94 end audio_single_pwm_v1_0_M00_AXI;
96 architecture implementation of audio_single_pwm_v1_0_M00_AXI is
98 -- function called clogb2 that returns an integer which has the
99 -- value of the ceiling of the log base 2
100 function clogb2 (bit_depth : integer) return integer is
101 variable depth : integer := bit_depth;
102 variable count : integer := 1;
104 for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
105 if (bit_depth <= 2) then
119 -- Example user application signals
121 -- TRANS_NUM_BITS is the width of the index counter for
122 -- number of write or read transaction..
123 constant TRANS_NUM_BITS : integer := clogb2(C_M_TRANSACTIONS_NUM-1);
125 -- Example State machine to initialize counter, initialize write transactions,
126 -- initialize read transactions and comparison of read data with the
127 -- written data words.
128 type state is ( IDLE, -- This state initiates AXI4Lite transaction
129 -- after the state machine changes state to INIT_WRITE
130 -- when there is 0 to 1 transition on INIT_AXI_TXN
131 INIT_WRITE, -- This state initializes write transaction,
132 -- once writes are done, the state machine
133 -- changes state to INIT_READ
134 INIT_READ, -- This state initializes read transaction
135 -- once reads are done, the state machine
136 -- changes state to INIT_COMPARE
137 INIT_COMPARE);-- This state issues the status of comparison
138 -- of the written data with the read data
140 signal mst_exec_state : state ;
143 --write address valid
144 signal axi_awvalid : std_logic;
146 signal axi_wvalid : std_logic;
148 signal axi_arvalid : std_logic;
149 --read data acceptance
150 signal axi_rready : std_logic;
151 --write response acceptance
152 signal axi_bready : std_logic;
154 signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
156 signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
158 signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
159 --Asserts when there is a write response error
160 signal write_resp_error : std_logic;
161 --Asserts when there is a read response error
162 signal read_resp_error : std_logic;
163 --A pulse to initiate a write transaction
164 signal start_single_write : std_logic;
165 --A pulse to initiate a read transaction
166 signal start_single_read : std_logic;
167 --Asserts when a single beat write transaction is issued and remains asserted till the completion of write trasaction.
168 signal write_issued : std_logic;
169 --Asserts when a single beat read transaction is issued and remains asserted till the completion of read trasaction.
170 signal read_issued : std_logic;
171 --flag that marks the completion of write trasactions. The number of write transaction is user selected by the parameter C_M_TRANSACTIONS_NUM.
172 signal writes_done : std_logic;
173 --flag that marks the completion of read trasactions. The number of read transaction is user selected by the parameter C_M_TRANSACTIONS_NUM
174 signal reads_done : std_logic;
175 --The error register is asserted when any of the write response error, read response error or the data mismatch flags are asserted.
176 signal error_reg : std_logic;
177 --index counter to track the number of write transaction issued
178 signal write_index : std_logic_vector(TRANS_NUM_BITS downto 0);
179 --index counter to track the number of read transaction issued
180 signal read_index : std_logic_vector(TRANS_NUM_BITS downto 0);
181 --Expected read data used to compare with the read data.
182 signal expected_rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
183 --Flag marks the completion of comparison of the read data with the expected read data
184 signal compare_done : std_logic;
185 --This flag is asserted when there is a mismatch of the read data with the expected read data.
186 signal read_mismatch : std_logic;
187 --Flag is asserted when the write index reaches the last write transction number
188 signal last_write : std_logic;
189 --Flag is asserted when the read index reaches the last read transction number
190 signal last_read : std_logic;
191 signal init_txn_ff : std_logic;
192 signal init_txn_ff2 : std_logic;
193 signal init_txn_edge : std_logic;
194 signal init_txn_pulse : std_logic;
198 -- I/O Connections assignments
200 --Adding the offset address to the base addr of the slave
201 M_AXI_AWADDR <= std_logic_vector (unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_awaddr));
203 M_AXI_WDATA <= axi_wdata;
204 M_AXI_AWPROT <= "000";
205 M_AXI_AWVALID <= axi_awvalid;
207 M_AXI_WVALID <= axi_wvalid;
208 --Set all byte strobes in this example
209 M_AXI_WSTRB <= "1111";
211 M_AXI_BREADY <= axi_bready;
213 M_AXI_ARADDR <= std_logic_vector(unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_araddr));
214 M_AXI_ARVALID <= axi_arvalid;
215 M_AXI_ARPROT <= "001";
216 --Read and Read Response (R)
217 M_AXI_RREADY <= axi_rready;
219 TXN_DONE <= compare_done;
220 init_txn_pulse <= ( not init_txn_ff2) and init_txn_ff;
223 --Generate a pulse to initiate AXI transaction.
226 if (rising_edge (M_AXI_ACLK)) then
227 -- Initiates AXI transaction delay
228 if (M_AXI_ARESETN = '0' ) then
232 init_txn_ff <= INIT_AXI_TXN;
233 init_txn_ff2 <= init_txn_ff;
239 ----------------------
240 --Write Address Channel
241 ----------------------
243 -- The purpose of the write address channel is to request the address and
244 -- command information for the entire transaction. It is a single beat
247 -- Note for this example the axi_awvalid/axi_wvalid are asserted at the same
248 -- time, and then each is deasserted independent from each other.
249 -- This is a lower-performance, but simplier control scheme.
251 -- AXI VALID signals must be held active until accepted by the partner.
253 -- A data transfer is accepted by the slave when a master has
254 -- VALID data and the slave acknoledges it is also READY. While the master
255 -- is allowed to generated multiple, back-to-back requests by not
256 -- deasserting VALID, this design will add rest cycle for
259 -- Since only one outstanding transaction is issued by the user design,
260 -- there will not be a collision between a new request and an accepted
261 -- request on the same clock cycle.
265 if (rising_edge (M_AXI_ACLK)) then
266 --Only VALID signals must be deasserted during reset per AXI spec
267 --Consider inverting then registering active-low reset for higher fmax
268 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
271 --Signal a new address/data command is available by user logic
272 if (start_single_write = '1') then
274 elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
275 --Address accepted by interconnect/slave (issue of M_AXI_AWREADY by slave)
282 -- start_single_write triggers a new write
283 -- transaction. write_index is a counter to
284 -- keep track with number of write transaction
288 if (rising_edge (M_AXI_ACLK)) then
289 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
290 write_index <= (others => '0');
291 elsif (start_single_write = '1') then
292 -- Signals a new write address/ write data is
293 -- available by user logic
294 write_index <= std_logic_vector (unsigned(write_index) + 1);
300 ----------------------
302 ----------------------
304 --The write data channel is for transfering the actual data.
305 --The data generation is speific to the example design, and
306 --so only the WVALID/WREADY handshake is shown here
310 if (rising_edge (M_AXI_ACLK)) then
311 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
314 if (start_single_write = '1') then
315 --Signal a new address/data command is available by user logic
317 elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
318 --Data accepted by interconnect/slave (issue of M_AXI_WREADY by slave)
326 ------------------------------
327 --Write Response (B) Channel
328 ------------------------------
330 --The write response channel provides feedback that the write has committed
331 --to memory. BREADY will occur after both the data and the write address
332 --has arrived and been accepted by the slave, and can guarantee that no
333 --other accesses launched afterwards will be able to be reordered before it.
335 --The BRESP bit [1] is used indicate any errors from the interconnect or
336 --slave for the entire write burst. This example will capture the error.
338 --While not necessary per spec, it is advisable to reset READY signals in
339 --case of differing reset latencies between master/slave.
343 if (rising_edge (M_AXI_ACLK)) then
344 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
347 if (M_AXI_BVALID = '1' and axi_bready = '0') then
348 -- accept/acknowledge bresp with axi_bready by the master
349 -- when M_AXI_BVALID is asserted by slave
351 elsif (axi_bready = '1') then
352 -- deassert after one clock cycle
359 write_resp_error <= (axi_bready and M_AXI_BVALID and M_AXI_BRESP(1));
362 ------------------------------
363 --Read Address Channel
364 ------------------------------
366 --start_single_read triggers a new read transaction. read_index is a counter to
367 --keep track with number of read transaction issued/initiated
371 if (rising_edge (M_AXI_ACLK)) then
372 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
373 read_index <= (others => '0');
375 if (start_single_read = '1') then
376 -- Signals a new read address is
377 -- available by user logic
378 read_index <= std_logic_vector (unsigned(read_index) + 1);
384 -- A new axi_arvalid is asserted when there is a valid read address
385 -- available by the master. start_single_read triggers a new read
389 if (rising_edge (M_AXI_ACLK)) then
390 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
393 if (start_single_read = '1') then
394 --Signal a new read address command is available by user logic
396 elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
397 --RAddress accepted by interconnect/slave (issue of M_AXI_ARREADY by slave)
405 ----------------------------------
406 --Read Data (and Response) Channel
407 ----------------------------------
409 --The Read Data channel returns the results of the read request
410 --The master will accept the read data by asserting axi_rready
411 --when there is a valid read data available.
412 --While not necessary per spec, it is advisable to reset READY signals in
413 --case of differing reset latencies between master/slave.
417 if (rising_edge (M_AXI_ACLK)) then
418 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
421 if (M_AXI_RVALID = '1' and axi_rready = '0') then
422 -- accept/acknowledge rdata/rresp with axi_rready by the master
423 -- when M_AXI_RVALID is asserted by slave
425 elsif (axi_rready = '1') then
426 -- deassert after one clock cycle
434 read_resp_error <= (axi_rready and M_AXI_RVALID and M_AXI_RRESP(1));
437 ----------------------------------
439 ----------------------------------
441 --Address/Data Stimulus
443 --Address/data pairs for this example. The read and write values should
445 --Modify these as desired for different address patterns.
450 if (rising_edge (M_AXI_ACLK)) then
451 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
452 axi_awaddr <= (others => '0');
453 elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
454 -- Signals a new write address/ write data is
455 -- available by user logic
456 axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) + 4);
464 if (rising_edge (M_AXI_ACLK)) then
465 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
466 axi_araddr <= (others => '0');
467 elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
468 -- Signals a new write address/ write data is
469 -- available by user logic
470 axi_araddr <= std_logic_vector (unsigned(axi_araddr) + 4);
478 if (rising_edge (M_AXI_ACLK)) then
479 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
480 axi_wdata <= C_M_START_DATA_VALUE;
481 elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
482 -- Signals a new write address/ write data is
483 -- available by user logic
484 axi_wdata <= std_logic_vector (unsigned(C_M_START_DATA_VALUE) + unsigned(write_index));
490 -- Expected read data
493 if (rising_edge (M_AXI_ACLK)) then
494 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
495 expected_rdata <= C_M_START_DATA_VALUE;
496 elsif (M_AXI_RVALID = '1' and axi_rready = '1') then
497 -- Signals a new write address/ write data is
498 -- available by user logic
499 expected_rdata <= std_logic_vector (unsigned(C_M_START_DATA_VALUE) + unsigned(read_index));
503 --implement master command interface state machine
504 MASTER_EXECUTION_PROC:process(M_AXI_ACLK)
506 if (rising_edge (M_AXI_ACLK)) then
507 if (M_AXI_ARESETN = '0' ) then
509 -- All the signals are ed default values under reset condition
510 mst_exec_state <= IDLE;
511 start_single_write <= '0';
513 start_single_read <= '0';
519 case (mst_exec_state) is
522 -- This state is responsible to initiate
523 -- AXI transaction when init_txn_pulse is asserted
524 if ( init_txn_pulse = '1') then
525 mst_exec_state <= INIT_WRITE;
529 mst_exec_state <= IDLE;
533 -- This state is responsible to issue start_single_write pulse to
534 -- initiate a write transaction. Write transactions will be
535 -- issued until last_write signal is asserted.
537 if (writes_done = '1') then
538 mst_exec_state <= INIT_READ;
540 mst_exec_state <= INIT_WRITE;
542 if (axi_awvalid = '0' and axi_wvalid = '0' and M_AXI_BVALID = '0' and
543 last_write = '0' and start_single_write = '0' and write_issued = '0') then
544 start_single_write <= '1';
546 elsif (axi_bready = '1') then
549 start_single_write <= '0'; --Negate to generate a pulse
554 -- This state is responsible to issue start_single_read pulse to
555 -- initiate a read transaction. Read transactions will be
556 -- issued until last_read signal is asserted.
558 if (reads_done = '1') then
559 mst_exec_state <= INIT_COMPARE;
561 mst_exec_state <= INIT_READ;
563 if (axi_arvalid = '0' and M_AXI_RVALID = '0' and last_read = '0' and
564 start_single_read = '0' and read_issued = '0') then
565 start_single_read <= '1';
567 elsif (axi_rready = '1') then
570 start_single_read <= '0'; --Negate to generate a pulse
575 -- This state is responsible to issue the state of comparison
576 -- of written data with the read data. If no error flags are set,
577 -- compare_done signal will be asseted to indicate success.
579 mst_exec_state <= IDLE;
583 mst_exec_state <= IDLE;
589 --Terminal write count
592 if (rising_edge (M_AXI_ACLK)) then
593 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
597 --The last write should be associated with a write address ready response
598 if (write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and M_AXI_AWREADY = '1') then
606 -- Check for last write completion.
608 -- This logic is to qualify the last write count with the final write
609 -- response. This demonstrates how to confirm that a write has been
614 if (rising_edge (M_AXI_ACLK)) then
615 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
619 if (last_write = '1' and M_AXI_BVALID = '1' and axi_bready = '1') then
620 --The writes_done should be associated with a bready response
631 --Terminal Read Count
635 if (rising_edge (M_AXI_ACLK)) then
636 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
639 if (read_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and (M_AXI_ARREADY = '1') ) then
640 --The last read should be associated with a read address ready response
649 -- Check for last read completion.
651 -- This logic is to qualify the last read count with the final read
656 if (rising_edge (M_AXI_ACLK)) then
657 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
660 if (last_read = '1' and M_AXI_RVALID = '1' and axi_rready = '1') then
661 --The reads_done should be associated with a read ready response
669 ------------------------------/
670 --Example design error register
671 ------------------------------/
676 if (rising_edge (M_AXI_ACLK)) then
677 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
678 read_mismatch <= '0';
680 if ((M_AXI_RVALID = '1' and axi_rready = '1') and M_AXI_RDATA /= expected_rdata) then
681 --The read data when available (on axi_rready) is compared with the expected data
682 read_mismatch <= '1';
688 -- Register and hold any data mismatches, or read/write interface errors
691 if (rising_edge (M_AXI_ACLK)) then
692 if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
695 if (read_mismatch = '1' or write_resp_error = '1' or read_resp_error = '1') then
696 --Capture any error types
703 -- Add user logic here