system/ip/dcsimpledrv_1.0/example_designs/bfm_design/dcsimpledrv_v1_0_tb.v

   1
   2 `timescale 1 ns / 1 ps
   3
   4 `include "dcsimpledrv_v1_0_tb_include.vh"
   5
   6 // lite_response Type Defines
   7 `define RESPONSE_OKAY 2'b00
   8 `define RESPONSE_EXOKAY 2'b01
   9 `define RESP_BUS_WIDTH 2
  10 `define BURST_TYPE_INCR  2'b01
  11 `define BURST_TYPE_WRAP  2'b10
  12
  13 // AMBA AXI4 Lite Range Constants
  14 `define S00_AXI_MAX_BURST_LENGTH 1
  15 `define S00_AXI_DATA_BUS_WIDTH 32
  16 `define S00_AXI_ADDRESS_BUS_WIDTH 32
  17 `define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
  18
  19 module dcsimpledrv_v1_0_tb;
  20         reg tb_ACLK;
  21         reg tb_ARESETn;
  22
  23         // Create an instance of the example tb
  24         `BD_WRAPPER dut (.ACLK(tb_ACLK),
  25                                 .ARESETN(tb_ARESETn));
  26
  27         // Local Variables
  28
  29         // AMBA S00_AXI AXI4 Lite Local Reg
  30         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
  31         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
  32         reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
  33         reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
  34         reg [3-1:0]   S00_AXI_mtestProtection_lite;
  35         integer S00_AXI_mtestvectorlite; // Master side testvector
  36         integer S00_AXI_mtestdatasizelite;
  37         integer result_slave_lite;
  38
  39
  40         // Simple Reset Generator and test
  41         initial begin
  42                 tb_ARESETn = 1'b0;
  43           #500;
  44                 // Release the reset on the posedge of the clk.
  45                 @(posedge tb_ACLK);
  46           tb_ARESETn = 1'b1;
  47                 @(posedge tb_ACLK);
  48         end
  49
  50         // Simple Clock Generator
  51         initial tb_ACLK = 1'b0;
  52         always #10 tb_ACLK = !tb_ACLK;
  53
  54         //------------------------------------------------------------------------
  55         // TEST LEVEL API: CHECK_RESPONSE_OKAY
  56         //------------------------------------------------------------------------
  57         // Description:
  58         // CHECK_RESPONSE_OKAY(lite_response)
  59         // This task checks if the return lite_response is equal to OKAY
  60         //------------------------------------------------------------------------
  61         task automatic CHECK_RESPONSE_OKAY;
  62                 input [`RESP_BUS_WIDTH-1:0] response;
  63                 begin
  64                   if (response !== `RESPONSE_OKAY) begin
  65                           $display("TESTBENCH ERROR! lite_response is not OKAY",
  66                                          "\n expected = 0x%h",`RESPONSE_OKAY,
  67                                          "\n actual   = 0x%h",response);
  68                     $stop;
  69                   end
  70                 end
  71         endtask
  72
  73         //------------------------------------------------------------------------
  74         // TEST LEVEL API: COMPARE_LITE_DATA
  75         //------------------------------------------------------------------------
  76         // Description:
  77         // COMPARE_LITE_DATA(expected,actual)
  78         // This task checks if the actual data is equal to the expected data.
  79         // X is used as don't care but it is not permitted for the full vector
  80         // to be don't care.
  81         //------------------------------------------------------------------------
  82         `define S_AXI_DATA_BUS_WIDTH 32
  83         task automatic COMPARE_LITE_DATA;
  84                 input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
  85                 input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
  86                 begin
  87                         if (expected === 'hx || actual === 'hx) begin
  88                                 $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
  89                     result_slave_lite = 0;
  90                     $stop;
  91                   end
  92
  93                         if (actual != expected) begin
  94                                 $display("TESTBENCH ERROR! Data expected is not equal to actual.",
  95                                          "\nexpected = 0x%h",expected,
  96                                          "\nactual   = 0x%h",actual);
  97                     result_slave_lite = 0;
  98                     $stop;
  99                   end
 100                         else
 101                         begin
 102                            $display("TESTBENCH Passed! Data expected is equal to actual.",
 103                                     "\n expected = 0x%h",expected,
 104                                     "\n actual   = 0x%h",actual);
 105                         end
 106                 end
 107         endtask
 108
 109         task automatic S00_AXI_TEST;
 110                 begin
 111                         $display("---------------------------------------------------------");
 112                         $display("EXAMPLE TEST : S00_AXI");
 113                         $display("Simple register write and read example");
 114                         $display("---------------------------------------------------------");
 115
 116                         S00_AXI_mtestvectorlite = 0;
 117                         S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
 118                         S00_AXI_mtestProtection_lite = 0;
 119                         S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
 120
 121                          result_slave_lite = 1;
 122
 123                         for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
 124                         begin
 125                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
 126                                                      S00_AXI_mtestProtection_lite,
 127                                                      S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
 128                                                      S00_AXI_mtestdatasizelite,
 129                                                      S00_AXI_lite_response);
 130                           $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
 131                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 132                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
 133                                                      S00_AXI_mtestProtection_lite,
 134                                                      S00_AXI_rd_data_lite,
 135                                                      S00_AXI_lite_response);
 136                           $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
 137                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 138                           COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
 139                           $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
 140                           S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
 141                         end
 142
 143                         $display("---------------------------------------------------------");
 144                         $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
 145                                 if ( result_slave_lite ) begin
 146                                         $display("PTGEN_TEST: PASSED!");
 147                                 end     else begin
 148                                         $display("PTGEN_TEST: FAILED!");
 149                                 end
 150                         $display("---------------------------------------------------------");
 151                 end
 152         endtask
 153
 154         // Create the test vectors
 155         initial begin
 156                 // When performing debug enable all levels of INFO messages.
 157                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 158                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 159                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 160                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 161                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 162
 163                 dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
 164
 165                 // Create test data vectors
 166                 S00_AXI_test_data_lite[0] = 32'h0101FFFF;
 167                 S00_AXI_test_data_lite[1] = 32'habcd0001;
 168                 S00_AXI_test_data_lite[2] = 32'hdead0011;
 169                 S00_AXI_test_data_lite[3] = 32'hbeef0011;
 170         end
 171
 172         // Drive the BFM
 173         initial begin
 174                 // Wait for end of reset
 175                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 176                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 177                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 178                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 179                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 180
 181                 S00_AXI_TEST();
 182
 183         end
 184
 185 endmodule